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1 ;; Machine Descriptions for R8C/M16C/M32C
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2 ;; Copyright (C) 2005, 2007
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Red Hat.
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ;; bit shifting
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23
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24 ; Shifts are unusual for m32c. We only support shifting in one
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25 ; "direction" but the shift count is signed. Also, immediate shift
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26 ; counts have a limited range, and variable shift counts have to be in
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27 ; $r1h which GCC normally doesn't even know about.
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28
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29 ; Other than compensating for the above, the patterns below are pretty
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30 ; straightforward.
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31
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32 (define_insn "ashlqi3_i"
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33 [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
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34 (ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
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35 (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
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36 (clobber (match_scratch:HI 3 "=X,R1w"))]
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37 ""
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38 "@
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39 sha.b\t%2,%0
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40 mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
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41 [(set_attr "flags" "oszc,oszc")]
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42 )
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43
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44 (define_insn "ashrqi3_i"
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45 [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
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46 (ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
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47 (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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48 (clobber (match_scratch:HI 3 "=X,R1w"))]
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49 ""
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50 "@
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51 sha.b\t%2,%0
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52 mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
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53 [(set_attr "flags" "oszc,oszc")]
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54 )
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55
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56 (define_insn "lshrqi3_i"
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57 [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
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58 (lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
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59 (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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60 (clobber (match_scratch:HI 3 "=X,R1w"))]
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61 ""
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62 "@
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63 shl.b\t%2,%0
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64 mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
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65 [(set_attr "flags" "szc,szc")]
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66 )
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67
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68
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69 (define_expand "ashlqi3"
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70 [(parallel [(set (match_operand:QI 0 "mra_operand" "")
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71 (ashift:QI (match_operand:QI 1 "mra_operand" "")
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72 (match_operand:QI 2 "general_operand" "")))
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73 (clobber (match_scratch:HI 3 ""))])]
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74 ""
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75 "if (m32c_prepare_shift (operands, 1, ASHIFT))
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76 DONE;"
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77 )
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78
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79 (define_expand "ashrqi3"
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80 [(parallel [(set (match_operand:QI 0 "mra_operand" "")
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81 (ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
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82 (neg:QI (match_operand:QI 2 "general_operand" ""))))
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83 (clobber (match_scratch:HI 3 ""))])]
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84 ""
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85 "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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86 DONE;"
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87 )
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88
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89 (define_expand "lshrqi3"
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90 [(parallel [(set (match_operand:QI 0 "mra_operand" "")
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91 (lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
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92 (neg:QI (match_operand:QI 2 "general_operand" ""))))
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93 (clobber (match_scratch:HI 3 ""))])]
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94 ""
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95 "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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96 DONE;"
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97 )
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98
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99 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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100
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101 (define_insn "ashlhi3_i"
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102 [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
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103 (ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
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104 (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
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105 (clobber (match_scratch:HI 3 "=X,R1w"))]
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106 ""
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107 "@
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108 sha.w\t%2,%0
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109 mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
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110 [(set_attr "flags" "oszc,oszc")]
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111 )
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112
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113 (define_insn "ashrhi3_i"
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114 [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
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115 (ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
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116 (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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117 (clobber (match_scratch:HI 3 "=X,R1w"))]
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118 ""
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119 "@
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120 sha.w\t%2,%0
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121 mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
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122 [(set_attr "flags" "oszc,oszc")]
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123 )
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124
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125 (define_insn "lshrhi3_i"
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126 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,RhiSd*Rmm")
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127 (lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
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128 (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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129 (clobber (match_scratch:HI 3 "=X,R1w"))]
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130 ""
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131 "@
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132 shl.w\t%2,%0
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133 mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
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134 [(set_attr "flags" "szc,szc")]
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135 )
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136
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137
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138 (define_expand "ashlhi3"
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139 [(parallel [(set (match_operand:HI 0 "mra_operand" "")
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140 (ashift:HI (match_operand:HI 1 "mra_operand" "")
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141 (match_operand:QI 2 "general_operand" "")))
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142 (clobber (match_scratch:HI 3 ""))])]
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143 ""
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144 "if (m32c_prepare_shift (operands, 1, ASHIFT))
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145 DONE;"
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146 )
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147
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148 (define_expand "ashrhi3"
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149 [(parallel [(set (match_operand:HI 0 "mra_operand" "")
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150 (ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
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151 (neg:QI (match_operand:QI 2 "general_operand" ""))))
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152 (clobber (match_scratch:HI 3 ""))])]
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153 ""
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154 "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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155 DONE;"
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156 )
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157
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158 (define_expand "lshrhi3"
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159 [(parallel [(set (match_operand:HI 0 "mra_operand" "")
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160 (lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
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161 (neg:QI (match_operand:QI 2 "general_operand" ""))))
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162 (clobber (match_scratch:HI 3 ""))])]
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163 ""
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164 "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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165 DONE;"
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166 )
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167
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168
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169
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170
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171 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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172
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173
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174 (define_insn "ashlpsi3_i"
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175 [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
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176 (ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
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177 (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
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178 (clobber (match_scratch:HI 3 "=X,R1w"))]
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179 "TARGET_A24"
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180 "@
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181 sha.l\t%2,%0
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182 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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183 [(set_attr "flags" "oszc,oszc")]
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184 )
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185
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186 (define_insn "ashrpsi3_i"
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187 [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
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188 (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
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189 (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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190 (clobber (match_scratch:HI 3 "=X,R1w"))]
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191 "TARGET_A24"
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192 "@
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193 sha.l\t%2,%0
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194 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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195 [(set_attr "flags" "oszc,oszc")]
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196 )
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197
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198 (define_insn "lshrpsi3_i"
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199 [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
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200 (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
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201 (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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202 (clobber (match_scratch:HI 3 "=X,R1w"))]
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203 "TARGET_A24"
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204 "@
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205 shl.l\t%2,%0
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206 mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
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207 [(set_attr "flags" "szc,szc")]
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208 )
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209
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210
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211 (define_expand "ashlpsi3"
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212 [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
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213 (ashift:PSI (match_operand:PSI 1 "mra_operand" "")
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214 (match_operand:QI 2 "shiftcount_operand" "")))
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215 (clobber (match_scratch:HI 3 ""))])]
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216 "TARGET_A24"
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217 "if (m32c_prepare_shift (operands, 1, ASHIFT))
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218 DONE;"
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219 )
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220
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221 (define_expand "ashrpsi3"
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222 [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
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223 (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
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224 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
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225 (clobber (match_scratch:HI 3 ""))])]
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226 "TARGET_A24"
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227 "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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228 DONE;"
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229 )
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230
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231 (define_expand "lshrpsi3"
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232 [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
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233 (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
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234 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
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235 (clobber (match_scratch:HI 3 ""))])]
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236 "TARGET_A24"
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237 "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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238 DONE;"
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239 )
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240
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241 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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242
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243 ; The m16c has a maximum shift count of -16..16, even when in a
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244 ; register. It's optimal to use multiple shifts of -8..8 rather than
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245 ; loading larger constants into R1H multiple time. The m32c can shift
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246 ; -32..32 either via immediates or in registers. Hence, separate
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247 ; patterns.
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248
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249
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250 (define_insn "ashlsi3_16"
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251 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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252 (ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
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253 (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
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254 (clobber (match_scratch:HI 3 "=X,R1w"))]
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255 "TARGET_A16"
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256 "@
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257 sha.l\t%2,%0
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258 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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259 [(set_attr "flags" "oszc,oszc")]
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260 )
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261
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262 (define_insn "ashrsi3_16"
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263 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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264 (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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265 (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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266 (clobber (match_scratch:HI 3 "=X,R1w"))]
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267 "TARGET_A16"
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268 "@
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269 sha.l\t%2,%0
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270 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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271 [(set_attr "flags" "oszc,oszc")]
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272 )
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273
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274 (define_insn "lshrsi3_16"
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275 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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276 (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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277 (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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278 (clobber (match_scratch:HI 3 "=X,R1w"))]
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279 "TARGET_A16"
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280 "@
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281 shl.l\t%2,%0
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282 mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
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283 [(set_attr "flags" "szc,szc")]
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284 )
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285
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286
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287
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288 (define_insn "ashlsi3_24"
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289 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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290 (ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
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291 (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd")))
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292 (clobber (match_scratch:HI 3 "=X,R1w"))]
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293 "TARGET_A24"
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294 "@
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295 sha.l\t%2,%0
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296 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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297 )
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298
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299 (define_insn "ashrsi3_24"
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300 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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301 (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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302 (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
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303 (clobber (match_scratch:HI 3 "=X,R1w"))]
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304 "TARGET_A24"
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305 "@
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306 sha.l\t%2,%0
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307 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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308 )
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309
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310 (define_insn "lshrsi3_24"
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311 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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312 (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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313 (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
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314 (clobber (match_scratch:HI 3 "=X,R1w"))]
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315 "TARGET_A24"
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316 "@
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317 shl.l\t%2,%0
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318 mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
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319 )
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320
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321
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322
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323
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324 (define_expand "ashlsi3"
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325 [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
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326 (ashift:SI (match_operand:SI 1 "r0123_operand" "")
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327 (match_operand:QI 2 "mrai_operand" "")))
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328 (clobber (match_scratch:HI 3 ""))])]
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329 ""
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330 "if (m32c_prepare_shift (operands, 1, ASHIFT))
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331 DONE;"
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332 )
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333
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334 (define_expand "ashrsi3"
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335 [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
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336 (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
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337 (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
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338 (clobber (match_scratch:HI 3 ""))])]
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339 ""
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340 "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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341 DONE;"
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342 )
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343
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344 (define_expand "lshrsi3"
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345 [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
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346 (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
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347 (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
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348 (clobber (match_scratch:HI 3 ""))])]
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349 ""
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350 "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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351 DONE;"
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352 )
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