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1 ;; Scheduling description for GR6.
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2 ;; Copyright (C) 2013-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; GR6 is a dual-issue, superscalar, out-of-order processor.
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21 ;;
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22 ;; The GR6 pipeline has 3 major components:
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23 ;; 1. The FETCH/DECODE/DISPATCH stages, an in-order front-end,
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24 ;; 2. The PROCESS stage, which is the out-of-order core,
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25 ;; 3. The STORE stage, an in-order register storage stage.
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26 ;;
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27 ;; The front-end and the back-end (PROCESS + STORE) are connected through a set
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28 ;; of reservation stations which, among other things, serve as buffers for the
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29 ;; decoded instructions. The reservation stations are attached to a specific
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30 ;; execution unit of the PROCESS stage and the DISPATCH stage is responsible
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31 ;; for dispatching the decoded instructions to the appropriate stations. Most
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32 ;; execution units have multiple reservation stations, thus making it possible
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33 ;; to dispatch two instructions per unit on a given cycle, but only one of them
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34 ;; can be executed on the next cycle.
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35 ;;
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36 ;; Since the core executes the instructions out of order, the most important
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37 ;; consideration for performance tuning is to make sure that enough decoded
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38 ;; instructions are ready for execution in the PROCESS stage while not stalling
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39 ;; the front-end, i.e while not trying to dispatch a decoded instruction to an
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40 ;; execution unit whose reservation stations are full. Therefore, we do not
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41 ;; model the reservation stations (which is equivalent to pretending that there
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42 ;; is only one of them for each execution unit) but only the execution unit,
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43 ;; thus preserving some margin in case the unit itself stalls unexpectedly.
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44
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45 ;; CPU execution units:
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46 ;;
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47 ;; inst[1|2] The front-end: 2 instructions can be issued on a given
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48 ;; cycle by the FETCH/DECODE/DISPATCH stages, except for
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49 ;; the Block Move instructions.
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50 ;;
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51 ;; mov Move Execution Unit: immediate moves into registers.
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52 ;;
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53 ;; alu[1|2] The 2 Arithmetic and Logic Units: other instructions
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54 ;; operating on the registers.
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55 ;;
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56 ;; bru Branch Resolution Unit: all branches.
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57 ;;
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58 ;; mem_wr Memory Write Unit: all writes to memory.
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59 ;;
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60 ;; mem_rd Memory Read Unit: all reads from memory.
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61 ;;
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62 ;; mem_eam EAM interface: reads and writes from and to the EAM
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63 ;; and reads from the FP registers.
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64 ;;
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65 ;; eam Extended Arithmetic Module: multiply, divide and
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66 ;; 64-bit shifts.
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67 ;;
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68 ;; fpcu Floating-Point Compare Unit: FP comparisons.
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69 ;;
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70 ;; fpu[1|2|3|4] The 4 Floating-Point Units: all other instructions
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71 ;; operating on the FP registers.
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72
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73 (define_automaton "gr6,gr6_fpu")
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74
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75 (define_cpu_unit "gr6_inst1, gr6_inst2" "gr6")
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76 (define_cpu_unit "gr6_mov" "gr6")
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77 (define_cpu_unit "gr6_alu1,gr6_alu2" "gr6")
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78 (define_cpu_unit "gr6_bru" "gr6")
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79 (define_cpu_unit "gr6_mem_wr,gr6_mem_rd,gr6_mem_eam" "gr6")
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80 (define_cpu_unit "gr6_eam" "gr6")
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81 (define_cpu_unit "gr6_fpcu" "gr6")
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82 (define_cpu_unit "gr6_fpu1,gr6_fpu2,gr6_fpu3,gr6_fpu4" "gr6_fpu")
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83
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84 (define_reservation "gr6_issue" "(gr6_inst1 | gr6_inst2)")
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85 (define_reservation "gr6_single_issue" "gr6_inst1 + gr6_inst2")
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86
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87 (define_insn_reservation "gr6_immediate" 1
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88 (and (eq_attr "cpu" "gr6")
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89 (eq_attr "type" "imm_reg"))
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90 "gr6_issue + gr6_mov")
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91
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92 (define_insn_reservation "gr6_alu" 1
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93 (and (eq_attr "cpu" "gr6")
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94 (eq_attr "type" "arith,arith2,logic,cmp"))
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95 "gr6_issue + (gr6_alu1 | gr6_alu2)")
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96
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97 (define_insn_reservation "gr6_branch" 1
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98 (and (eq_attr "cpu" "gr6")
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99 (eq_attr "type" "abs_branch,branch,call,ret,rfi"))
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100 "gr6_issue + gr6_bru")
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101
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102 (define_insn_reservation "gr6_block_move" 16
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103 (and (eq_attr "cpu" "gr6")
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104 (eq_attr "type" "bmi"))
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105 "gr6_single_issue*16")
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106
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107 (define_insn_reservation "gr6_cpu_other" 1
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108 (and (eq_attr "cpu" "gr6")
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109 (eq_attr "type" "dsi,nop"))
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110 "gr6_issue")
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111
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112 (define_insn_reservation "gr6_write_mem" 1
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113 (and (eq_attr "cpu" "gr6")
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114 (eq_attr "type" "reg_mem"))
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115 "gr6_issue + gr6_mem_wr")
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116
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117 (define_insn_reservation "gr6_read_mem" 6
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118 (and (eq_attr "cpu" "gr6")
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119 (eq_attr "type" "mem_reg"))
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120 "gr6_issue + gr6_mem_rd, nothing*5")
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121
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122 ;; EAM instructions.
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123
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124 (define_insn_reservation "gr6_write_eam" 2
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125 (and (eq_attr "cpu" "gr6")
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126 (eq_attr "type" "reg_eam"))
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127 "gr6_issue + gr6_mem_eam, nothing")
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128
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129 (define_reservation "gr6_issue_eam" "gr6_issue + gr6_mem_eam + gr6_eam")
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130
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131 (define_insn_reservation "gr6_read_eam" 2
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132 (and (eq_attr "cpu" "gr6")
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133 (eq_attr "type" "eam_reg"))
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134 "gr6_issue_eam, nothing")
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135
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136 (define_insn_reservation "gr6_shiftdi" 2
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137 (and (eq_attr "cpu" "gr6")
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138 (eq_attr "type" "shiftdi"))
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139 "gr6_issue_eam, gr6_eam")
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140
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141 (define_insn_reservation "gr6_mul" 3
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142 (and (eq_attr "cpu" "gr6")
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143 (eq_attr "type" "mul"))
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144 "gr6_issue_eam, gr6_eam*2")
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145
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146 (define_insn_reservation "gr6_div" 34
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147 (and (eq_attr "cpu" "gr6")
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148 (eq_attr "type" "div"))
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149 "gr6_issue_eam, gr6_eam*33")
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150
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151 (define_insn_reservation "gr6_divd" 66
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152 (and (eq_attr "cpu" "gr6")
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153 (eq_attr "type" "divd"))
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154 "gr6_issue_eam, gr6_eam*65")
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155
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156 ;; FPU instructions.
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157
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158 (define_insn_reservation "gr6_read_fp" 2
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159 (and (eq_attr "cpu" "gr6")
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160 (eq_attr "type" "fp_reg"))
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161 "gr6_issue + gr6_mem_eam, nothing")
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162
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163 (define_insn_reservation "gr6_cmp_fp" 1
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164 (and (eq_attr "cpu" "gr6")
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165 (eq_attr "type" "fcmp"))
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166 "gr6_issue + gr6_fpcu")
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167
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168 (define_insn_reservation "gr6_fp_1cycle" 1
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169 (and (eq_attr "cpu" "gr6")
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170 (eq_attr "type" "fmove,ftoi,itof"))
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171 "gr6_issue + gr6_fpu1")
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172
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173 (define_insn_reservation "gr6_fp_3cycle" 3
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174 (and (eq_attr "cpu" "gr6")
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175 (eq_attr "type" "fp"))
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176 "gr6_issue + gr6_fpu2, nothing*2")
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177
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178 (define_insn_reservation "gr6_fp_17cycle" 17
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179 (and (eq_attr "cpu" "gr6")
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180 (eq_attr "type" "fdiv,fsqrt"))
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181 "gr6_issue + gr6_fpu3, gr6_fpu3*14, nothing*2")
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182
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183 (define_insn_reservation "gr6_write_fp" 1
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184 (and (eq_attr "cpu" "gr6")
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185 (eq_attr "type" "reg_fp"))
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186 "gr6_issue + gr6_fpu4")
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