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1 /* Local Register Allocator (LRA) intercommunication header file.
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2 Copyright (C) 2010-2020 Free Software Foundation, Inc.
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3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it under
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8 the terms of the GNU General Public License as published by the Free
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9 Software Foundation; either version 3, or (at your option) any later
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10 version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 #ifndef GCC_LRA_INT_H
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22 #define GCC_LRA_INT_H
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23
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24 #define lra_assert(c) gcc_checking_assert (c)
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25
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26 /* The parameter used to prevent infinite reloading for an insn. Each
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27 insn operands might require a reload and, if it is a memory, its
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28 base and index registers might require a reload too. */
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29 #define LRA_MAX_INSN_RELOADS (MAX_RECOG_OPERANDS * 3)
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30
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31 typedef struct lra_live_range *lra_live_range_t;
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32
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33 /* The structure describes program points where a given pseudo lives.
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34 The live ranges can be used to find conflicts with other pseudos.
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35 If the live ranges of two pseudos are intersected, the pseudos are
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36 in conflict. */
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37 struct lra_live_range
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38 {
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39 /* Pseudo regno whose live range is described by given
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40 structure. */
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41 int regno;
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42 /* Program point range. */
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43 int start, finish;
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44 /* Next structure describing program points where the pseudo
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45 lives. */
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46 lra_live_range_t next;
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47 /* Pointer to structures with the same start. */
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48 lra_live_range_t start_next;
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49 };
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50
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51 typedef struct lra_copy *lra_copy_t;
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52
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53 /* Copy between pseudos which affects assigning hard registers. */
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54 struct lra_copy
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55 {
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56 /* True if regno1 is the destination of the copy. */
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57 bool regno1_dest_p;
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58 /* Execution frequency of the copy. */
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59 int freq;
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60 /* Pseudos connected by the copy. REGNO1 < REGNO2. */
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61 int regno1, regno2;
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62 /* Next copy with correspondingly REGNO1 and REGNO2. */
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63 lra_copy_t regno1_next, regno2_next;
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64 };
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65
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66 /* Common info about a register (pseudo or hard register). */
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67 class lra_reg
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68 {
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69 public:
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70 /* Bitmap of UIDs of insns (including debug insns) referring the
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71 reg. */
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72 bitmap_head insn_bitmap;
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73 /* The following fields are defined only for pseudos. */
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74 /* Hard registers with which the pseudo conflicts. */
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75 HARD_REG_SET conflict_hard_regs;
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76 /* We assign hard registers to reload pseudos which can occur in few
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77 places. So two hard register preferences are enough for them.
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78 The following fields define the preferred hard registers. If
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79 there are no such hard registers the first field value is
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80 negative. If there is only one preferred hard register, the 2nd
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81 field is negative. */
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82 int preferred_hard_regno1, preferred_hard_regno2;
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83 /* Profits to use the corresponding preferred hard registers. If
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84 the both hard registers defined, the first hard register has not
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85 less profit than the second one. */
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86 int preferred_hard_regno_profit1, preferred_hard_regno_profit2;
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87 #ifdef STACK_REGS
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88 /* True if the pseudo should not be assigned to a stack register. */
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89 bool no_stack_p;
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90 #endif
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91 /* Number of references and execution frequencies of the register in
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92 *non-debug* insns. */
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93 int nrefs, freq;
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94 int last_reload;
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95 /* rtx used to undo the inheritance. It can be non-null only
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96 between subsequent inheritance and undo inheritance passes. */
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97 rtx restore_rtx;
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98 /* Value holding by register. If the pseudos have the same value
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99 they do not conflict. */
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100 int val;
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101 /* Offset from relative eliminate register to pesudo reg. */
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102 poly_int64 offset;
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103 /* These members are set up in lra-lives.c and updated in
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104 lra-coalesce.c. */
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105 /* The biggest size mode in which each pseudo reg is referred in
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106 whole function (possibly via subreg). */
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107 machine_mode biggest_mode;
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108 /* Live ranges of the pseudo. */
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109 lra_live_range_t live_ranges;
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110 /* This member is set up in lra-lives.c for subsequent
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111 assignments. */
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112 lra_copy_t copies;
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113 };
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114
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115 /* References to the common info about each register. */
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116 extern class lra_reg *lra_reg_info;
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117
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118 extern HARD_REG_SET hard_regs_spilled_into;
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119
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120 /* Static info about each insn operand (common for all insns with the
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121 same ICODE). Warning: if the structure definition is changed, the
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122 initializer for debug_operand_data in lra.c should be changed
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123 too. */
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124 struct lra_operand_data
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125 {
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126 /* The machine description constraint string of the operand. */
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127 const char *constraint;
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128 /* Alternatives for which early_clobber can be true. */
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129 alternative_mask early_clobber_alts;
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130 /* It is taken only from machine description (which is different
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131 from recog_data.operand_mode) and can be of VOIDmode. */
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132 ENUM_BITFIELD(machine_mode) mode : 16;
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133 /* The type of the operand (in/out/inout). */
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134 ENUM_BITFIELD (op_type) type : 8;
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135 /* Through if accessed through STRICT_LOW. */
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136 unsigned int strict_low : 1;
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137 /* True if the operand is an operator. */
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138 unsigned int is_operator : 1;
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139 /* True if the operand is an address. */
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140 unsigned int is_address : 1;
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141 };
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142
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143 /* Info about register occurrence in an insn. */
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144 struct lra_insn_reg
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145 {
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146 /* Alternatives for which early_clobber can be true. */
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147 alternative_mask early_clobber_alts;
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148 /* The biggest mode through which the insn refers to the register
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149 occurrence (remember the register can be accessed through a
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150 subreg in the insn). */
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151 ENUM_BITFIELD(machine_mode) biggest_mode : 16;
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152 /* The type of the corresponding operand which is the register. */
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153 ENUM_BITFIELD (op_type) type : 8;
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154 /* True if the reg is accessed through a subreg and the subreg is
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155 just a part of the register. */
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156 unsigned int subreg_p : 1;
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157 /* The corresponding regno of the register. */
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158 int regno;
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159 /* Next reg info of the same insn. */
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160 struct lra_insn_reg *next;
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161 };
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162
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163 /* Static part (common info for insns with the same ICODE) of LRA
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164 internal insn info. It exists in at most one exemplar for each
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165 non-negative ICODE. There is only one exception. Each asm insn has
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166 own structure. Warning: if the structure definition is changed,
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167 the initializer for debug_insn_static_data in lra.c should be
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168 changed too. */
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169 struct lra_static_insn_data
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170 {
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171 /* Static info about each insn operand. */
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172 struct lra_operand_data *operand;
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173 /* Each duplication refers to the number of the corresponding
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174 operand which is duplicated. */
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175 int *dup_num;
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176 /* The number of an operand marked as commutative, -1 otherwise. */
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177 int commutative;
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178 /* Number of operands, duplications, and alternatives of the
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179 insn. */
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180 char n_operands;
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181 char n_dups;
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182 char n_alternatives;
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183 /* Insns in machine description (or clobbers in asm) may contain
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184 explicit hard regs which are not operands. The following list
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185 describes such hard registers. */
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186 struct lra_insn_reg *hard_regs;
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187 /* Array [n_alternatives][n_operand] of static constraint info for
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188 given operand in given alternative. This info can be changed if
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189 the target reg info is changed. */
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190 const struct operand_alternative *operand_alternative;
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191 };
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192
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131
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193 /* Negative insn alternative numbers used for special cases. */
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194 #define LRA_UNKNOWN_ALT -1
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195 #define LRA_NON_CLOBBERED_ALT -2
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196
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197 /* LRA internal info about an insn (LRA internal insn
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198 representation). */
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199 class lra_insn_recog_data
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200 {
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201 public:
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202 /* The insn code. */
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203 int icode;
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204 /* The alternative should be used for the insn, LRA_UNKNOWN_ALT if
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205 unknown, or we should assume any alternative, or the insn is a
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206 debug insn. LRA_NON_CLOBBERED_ALT means ignoring any earlier
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207 clobbers for the insn. */
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208 int used_insn_alternative;
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209 /* SP offset before the insn relative to one at the func start. */
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210 poly_int64 sp_offset;
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211 /* The insn itself. */
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212 rtx_insn *insn;
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213 /* Common data for insns with the same ICODE. Asm insns (their
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214 ICODE is negative) do not share such structures. */
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215 struct lra_static_insn_data *insn_static_data;
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216 /* Two arrays of size correspondingly equal to the operand and the
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217 duplication numbers: */
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218 rtx **operand_loc; /* The operand locations, NULL if no operands. */
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219 rtx **dup_loc; /* The dup locations, NULL if no dups. */
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220 /* Number of hard registers implicitly used/clobbered in given call
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221 insn. The value can be NULL or points to array of the hard
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222 register numbers ending with a negative value. To differ
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223 clobbered and used hard regs, clobbered hard regs are incremented
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224 by FIRST_PSEUDO_REGISTER. */
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225 int *arg_hard_regs;
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226 /* Cached value of get_preferred_alternatives. */
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227 alternative_mask preferred_alternatives;
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228 /* The following member value is always NULL for a debug insn. */
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229 struct lra_insn_reg *regs;
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230 };
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231
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232 typedef class lra_insn_recog_data *lra_insn_recog_data_t;
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233
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234 /* Whether the clobber is used temporary in LRA. */
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235 #define LRA_TEMP_CLOBBER_P(x) \
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236 (RTL_FLAG_CHECK1 ("TEMP_CLOBBER_P", (x), CLOBBER)->unchanging)
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237
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238 /* Cost factor for each additional reload and maximal cost reject for
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239 insn reloads. One might ask about such strange numbers. Their
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240 values occurred historically from former reload pass. */
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241 #define LRA_LOSER_COST_FACTOR 6
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242 #define LRA_MAX_REJECT 600
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243
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244 /* Maximum allowed number of assignment pass iterations after the
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245 latest spill pass when any former reload pseudo was spilled. It is
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246 for preventing LRA cycling in a bug case. */
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247 #define LRA_MAX_ASSIGNMENT_ITERATION_NUMBER 30
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248
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249 /* The maximal number of inheritance/split passes in LRA. It should
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250 be more 1 in order to perform caller saves transformations and much
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251 less MAX_CONSTRAINT_ITERATION_NUMBER to prevent LRA to do as many
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252 as permitted constraint passes in some complicated cases. The
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253 first inheritance/split pass has a biggest impact on generated code
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254 quality. Each subsequent affects generated code in less degree.
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255 For example, the 3rd pass does not change generated SPEC2000 code
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256 at all on x86-64. */
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257 #define LRA_MAX_INHERITANCE_PASSES 2
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258
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259 #if LRA_MAX_INHERITANCE_PASSES <= 0 \
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260 || LRA_MAX_INHERITANCE_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8
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261 #error wrong LRA_MAX_INHERITANCE_PASSES value
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262 #endif
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263
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264 /* Analogous macro to the above one but for rematerialization. */
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265 #define LRA_MAX_REMATERIALIZATION_PASSES 2
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266
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267 #if LRA_MAX_REMATERIALIZATION_PASSES <= 0 \
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268 || LRA_MAX_REMATERIALIZATION_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8
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269 #error wrong LRA_MAX_REMATERIALIZATION_PASSES value
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270 #endif
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271
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272 /* lra.c: */
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273
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274 extern FILE *lra_dump_file;
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275
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276 extern bool lra_asm_error_p;
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277 extern bool lra_reg_spill_p;
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278
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279 extern HARD_REG_SET lra_no_alloc_regs;
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280
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281 extern int lra_insn_recog_data_len;
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282 extern lra_insn_recog_data_t *lra_insn_recog_data;
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283
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284 extern int lra_curr_reload_num;
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285
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286 extern void lra_dump_bitmap_with_title (const char *, bitmap, int);
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287 extern hashval_t lra_rtx_hash (rtx x);
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288 extern void lra_push_insn (rtx_insn *);
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289 extern void lra_push_insn_by_uid (unsigned int);
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290 extern void lra_push_insn_and_update_insn_regno_info (rtx_insn *);
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291 extern rtx_insn *lra_pop_insn (void);
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292 extern unsigned int lra_insn_stack_length (void);
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293
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294 extern rtx lra_create_new_reg_with_unique_value (machine_mode, rtx,
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295 enum reg_class, const char *);
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296 extern void lra_set_regno_unique_value (int);
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297 extern void lra_invalidate_insn_data (rtx_insn *);
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298 extern void lra_set_insn_deleted (rtx_insn *);
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299 extern void lra_delete_dead_insn (rtx_insn *);
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300 extern void lra_emit_add (rtx, rtx, rtx);
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301 extern void lra_emit_move (rtx, rtx);
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302 extern void lra_update_dups (lra_insn_recog_data_t, signed char *);
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303
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304 extern void lra_process_new_insns (rtx_insn *, rtx_insn *, rtx_insn *,
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305 const char *);
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306
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131
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307 extern bool lra_substitute_pseudo (rtx *, int, rtx, bool, bool);
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308 extern bool lra_substitute_pseudo_within_insn (rtx_insn *, int, rtx, bool);
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309
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310 extern lra_insn_recog_data_t lra_set_insn_recog_data (rtx_insn *);
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311 extern lra_insn_recog_data_t lra_update_insn_recog_data (rtx_insn *);
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312 extern void lra_set_used_insn_alternative (rtx_insn *, int);
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313 extern void lra_set_used_insn_alternative_by_uid (int, int);
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314
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315 extern void lra_invalidate_insn_regno_info (rtx_insn *);
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316 extern void lra_update_insn_regno_info (rtx_insn *);
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317 extern struct lra_insn_reg *lra_get_insn_regs (int);
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318
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319 extern void lra_free_copies (void);
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320 extern void lra_create_copy (int, int, int);
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321 extern lra_copy_t lra_get_copy (int);
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322 extern bool lra_former_scratch_p (int);
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323 extern bool lra_former_scratch_operand_p (rtx_insn *, int);
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145
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324 extern void lra_register_new_scratch_op (rtx_insn *, int, int);
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111
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325
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326 extern int lra_new_regno_start;
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327 extern int lra_constraint_new_regno_start;
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328 extern int lra_bad_spill_regno_start;
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329 extern bitmap_head lra_inheritance_pseudos;
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330 extern bitmap_head lra_split_regs;
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331 extern bitmap_head lra_subreg_reload_pseudos;
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332 extern bitmap_head lra_optional_reload_pseudos;
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333
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334 /* lra-constraints.c: */
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335
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336 extern void lra_init_equiv (void);
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337 extern int lra_constraint_offset (int, machine_mode);
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338
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339 extern int lra_constraint_iter;
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145
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340 extern bool check_and_force_assignment_correctness_p;
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111
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341 extern int lra_inheritance_iter;
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342 extern int lra_undo_inheritance_iter;
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343 extern bool lra_constrain_insn (rtx_insn *);
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344 extern bool lra_constraints (bool);
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345 extern void lra_constraints_init (void);
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346 extern void lra_constraints_finish (void);
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131
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347 extern bool spill_hard_reg_in_range (int, enum reg_class, rtx_insn *, rtx_insn *);
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111
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348 extern void lra_inheritance (void);
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349 extern bool lra_undo_inheritance (void);
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350
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351 /* lra-lives.c: */
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352
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353 extern int lra_live_max_point;
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354 extern int *lra_point_freq;
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355
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356 extern int lra_hard_reg_usage[FIRST_PSEUDO_REGISTER];
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357
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358 extern int lra_live_range_iter;
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359 extern void lra_create_live_ranges (bool, bool);
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360 extern lra_live_range_t lra_copy_live_range_list (lra_live_range_t);
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361 extern lra_live_range_t lra_merge_live_ranges (lra_live_range_t,
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362 lra_live_range_t);
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363 extern bool lra_intersected_live_ranges_p (lra_live_range_t,
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364 lra_live_range_t);
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365 extern void lra_print_live_range_list (FILE *, lra_live_range_t);
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366 extern void debug (lra_live_range &ref);
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367 extern void debug (lra_live_range *ptr);
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368 extern void lra_debug_live_range_list (lra_live_range_t);
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369 extern void lra_debug_pseudo_live_ranges (int);
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370 extern void lra_debug_live_ranges (void);
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371 extern void lra_clear_live_ranges (void);
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372 extern void lra_live_ranges_init (void);
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373 extern void lra_live_ranges_finish (void);
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374 extern void lra_setup_reload_pseudo_preferenced_hard_reg (int, int, int);
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375
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376 /* lra-assigns.c: */
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377
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378 extern int lra_assignment_iter;
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379 extern int lra_assignment_iter_after_spill;
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380 extern void lra_setup_reg_renumber (int, int, bool);
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131
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381 extern bool lra_assign (bool &);
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382 extern bool lra_split_hard_reg_for (void);
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111
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383
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384 /* lra-coalesce.c: */
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385
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386 extern int lra_coalesce_iter;
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387 extern bool lra_coalesce (void);
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388
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389 /* lra-spills.c: */
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390
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145
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391 extern bool lra_need_for_scratch_reg_p (void);
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111
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392 extern bool lra_need_for_spills_p (void);
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393 extern void lra_spill (void);
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394 extern void lra_final_code_change (void);
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395
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396 /* lra-remat.c: */
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397
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398 extern int lra_rematerialization_iter;
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399 extern bool lra_remat (void);
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400
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401 /* lra-elimination.c: */
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402
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403 extern void lra_debug_elim_table (void);
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404 extern int lra_get_elimination_hard_regno (int);
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405 extern rtx lra_eliminate_regs_1 (rtx_insn *, rtx, machine_mode,
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131
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406 bool, bool, poly_int64, bool);
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407 extern void eliminate_regs_in_insn (rtx_insn *insn, bool, bool, poly_int64);
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111
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408 extern void lra_eliminate (bool, bool);
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409
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410 extern void lra_eliminate_reg_if_possible (rtx *);
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411
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412
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413
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414 /* Return the hard register which given pseudo REGNO assigned to.
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415 Negative value means that the register got memory or we don't know
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416 allocation yet. */
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417 static inline int
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418 lra_get_regno_hard_regno (int regno)
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419 {
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420 resize_reg_info ();
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421 return reg_renumber[regno];
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422 }
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423
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424 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
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425 using TITLE. Output a new line if NL_P. */
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426 static void inline
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427 lra_change_class (int regno, enum reg_class new_class,
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428 const char *title, bool nl_p)
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429 {
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430 lra_assert (regno >= FIRST_PSEUDO_REGISTER);
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431 if (lra_dump_file != NULL)
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432 fprintf (lra_dump_file, "%s class %s for r%d",
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433 title, reg_class_names[new_class], regno);
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434 setup_reg_classes (regno, new_class, NO_REGS, new_class);
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435 if (lra_dump_file != NULL && nl_p)
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436 fprintf (lra_dump_file, "\n");
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437 }
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438
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439 /* Update insn operands which are duplication of NOP operand. The
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440 insn is represented by its LRA internal representation ID. */
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441 static inline void
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442 lra_update_dup (lra_insn_recog_data_t id, int nop)
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443 {
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444 int i;
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445 struct lra_static_insn_data *static_id = id->insn_static_data;
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446
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447 for (i = 0; i < static_id->n_dups; i++)
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448 if (static_id->dup_num[i] == nop)
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449 *id->dup_loc[i] = *id->operand_loc[nop];
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450 }
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451
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452 /* Process operator duplications in insn with ID. We do it after the
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453 operands processing. Generally speaking, we could do this probably
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454 simultaneously with operands processing because a common practice
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455 is to enumerate the operators after their operands. */
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456 static inline void
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457 lra_update_operator_dups (lra_insn_recog_data_t id)
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458 {
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459 int i;
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460 struct lra_static_insn_data *static_id = id->insn_static_data;
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461
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462 for (i = 0; i < static_id->n_dups; i++)
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463 {
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464 int ndup = static_id->dup_num[i];
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465
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466 if (static_id->operand[ndup].is_operator)
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467 *id->dup_loc[i] = *id->operand_loc[ndup];
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468 }
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469 }
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470
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471 /* Return info about INSN. Set up the info if it is not done yet. */
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472 static inline lra_insn_recog_data_t
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473 lra_get_insn_recog_data (rtx_insn *insn)
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474 {
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475 lra_insn_recog_data_t data;
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476 unsigned int uid = INSN_UID (insn);
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477
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478 if (lra_insn_recog_data_len > (int) uid
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479 && (data = lra_insn_recog_data[uid]) != NULL)
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480 {
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481 /* Check that we did not change insn without updating the insn
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482 info. */
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483 lra_assert (data->insn == insn
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484 && (INSN_CODE (insn) < 0
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485 || data->icode == INSN_CODE (insn)));
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486 return data;
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487 }
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488 return lra_set_insn_recog_data (insn);
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489 }
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490
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491 /* Update offset from pseudos with VAL by INCR. */
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492 static inline void
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131
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493 lra_update_reg_val_offset (int val, poly_int64 incr)
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111
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494 {
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495 int i;
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496
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497 for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
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498 {
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499 if (lra_reg_info[i].val == val)
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500 lra_reg_info[i].offset += incr;
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501 }
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502 }
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503
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504 /* Return true if register content is equal to VAL with OFFSET. */
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505 static inline bool
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131
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506 lra_reg_val_equal_p (int regno, int val, poly_int64 offset)
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111
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507 {
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508 if (lra_reg_info[regno].val == val
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131
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509 && known_eq (lra_reg_info[regno].offset, offset))
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111
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510 return true;
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511
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512 return false;
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513 }
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514
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515 /* Assign value of register FROM to TO. */
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516 static inline void
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517 lra_assign_reg_val (int from, int to)
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518 {
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519 lra_reg_info[to].val = lra_reg_info[from].val;
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520 lra_reg_info[to].offset = lra_reg_info[from].offset;
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521 }
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522
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523 #endif /* GCC_LRA_INT_H */
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