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1 /* This file contains the exception-handling save_world and
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2 * restore_world routines, which need to do a run-time check to see if
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3 * they should save and restore the vector registers.
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4 *
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5 * Copyright (C) 2004, 2009 Free Software Foundation, Inc.
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6 *
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7 * This file is free software; you can redistribute it and/or modify it
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8 * under the terms of the GNU General Public License as published by the
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9 * Free Software Foundation; either version 3, or (at your option) any
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10 * later version.
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11 *
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12 * This file is distributed in the hope that it will be useful, but
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13 * WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 * General Public License for more details.
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16 *
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17 * Under Section 7 of GPL version 3, you are granted additional
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18 * permissions described in the GCC Runtime Library Exception, version
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19 * 3.1, as published by the Free Software Foundation.
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20 *
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21 * You should have received a copy of the GNU General Public License and
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22 * a copy of the GCC Runtime Library Exception along with this program;
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23 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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24 * <http://www.gnu.org/licenses/>.
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25 */
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26
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27 .machine ppc7400
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28 .data
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29 .align 2
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30
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31 #ifdef __DYNAMIC__
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32
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33 .non_lazy_symbol_pointer
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34 L_has_vec$non_lazy_ptr:
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35 .indirect_symbol __cpu_has_altivec
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36 #ifdef __ppc64__
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37 .quad 0
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38 #else
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39 .long 0
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40 #endif
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41
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42 #else
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43
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44 /* For static, "pretend" we have a non-lazy-pointer. */
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45
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46 L_has_vec$non_lazy_ptr:
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47 .long __cpu_has_altivec
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48
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49 #endif
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50
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51
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52 .text
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53 .align 2
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54
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55 /* save_world and rest_world save/restore F14-F31 and possibly V20-V31
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56 (assuming you have a CPU with vector registers; we use a global var
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57 provided by the System Framework to determine this.)
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58
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59 SAVE_WORLD takes R0 (the caller`s caller`s return address) and R11
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60 (the stack frame size) as parameters. It returns VRsave in R0 if
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61 we`re on a CPU with vector regs.
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62
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63 With gcc3, we now need to save and restore CR as well, since gcc3's
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64 scheduled prologs can cause comparisons to be moved before calls to
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65 save_world!
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66
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67 USES: R0 R11 R12 */
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68
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69 .private_extern save_world
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70 save_world:
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71 stw r0,8(r1)
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72 mflr r0
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73 bcl 20,31,Ls$pb
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74 Ls$pb: mflr r12
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75 addis r12,r12,ha16(L_has_vec$non_lazy_ptr-Ls$pb)
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76 lwz r12,lo16(L_has_vec$non_lazy_ptr-Ls$pb)(r12)
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77 mtlr r0
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78 lwz r12,0(r12)
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79 /* grab CR */
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80 mfcr r0
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81 /* test HAS_VEC */
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82 cmpwi r12,0
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83 stfd f14,-144(r1)
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84 stfd f15,-136(r1)
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85 stfd f16,-128(r1)
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86 stfd f17,-120(r1)
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87 stfd f18,-112(r1)
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88 stfd f19,-104(r1)
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89 stfd f20,-96(r1)
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90 stfd f21,-88(r1)
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91 stfd f22,-80(r1)
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92 stfd f23,-72(r1)
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93 stfd f24,-64(r1)
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94 stfd f25,-56(r1)
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95 stfd f26,-48(r1)
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96 stfd f27,-40(r1)
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97 stfd f28,-32(r1)
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98 stfd f29,-24(r1)
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99 stfd f30,-16(r1)
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100 stfd f31,-8(r1)
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101 stmw r13,-220(r1)
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102 /* stash CR */
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103 stw r0,4(r1)
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104 /* set R12 pointing at Vector Reg save area */
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105 addi r12,r1,-224
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106 /* allocate stack frame */
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107 stwux r1,r1,r11
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108 /* ...but return if HAS_VEC is zero */
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109 bne+ L$saveVMX
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110 /* Not forgetting to restore CR. */
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111 mtcr r0
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112 blr
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113
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114 L$saveVMX:
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115 /* We're saving Vector regs too. */
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116 /* Restore CR from R0. No More Branches! */
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117 mtcr r0
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118
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119 /* We should really use VRSAVE to figure out which vector regs
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120 we actually need to save and restore. Some other time :-/ */
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121
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122 li r11,-192
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123 stvx v20,r11,r12
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124 li r11,-176
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125 stvx v21,r11,r12
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126 li r11,-160
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127 stvx v22,r11,r12
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128 li r11,-144
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129 stvx v23,r11,r12
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130 li r11,-128
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131 stvx v24,r11,r12
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132 li r11,-112
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133 stvx v25,r11,r12
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134 li r11,-96
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135 stvx v26,r11,r12
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136 li r11,-80
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137 stvx v27,r11,r12
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138 li r11,-64
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139 stvx v28,r11,r12
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140 li r11,-48
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141 stvx v29,r11,r12
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142 li r11,-32
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143 stvx v30,r11,r12
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144 mfspr r0,VRsave
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145 li r11,-16
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146 stvx v31,r11,r12
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147 /* VRsave lives at -224(R1) */
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148 stw r0,0(r12)
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149 blr
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150
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151
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152 /* eh_rest_world_r10 is jumped to, not called, so no need to worry about LR.
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153 R10 is the C++ EH stack adjust parameter, we return to the caller`s caller.
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154
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155 USES: R0 R10 R11 R12 and R7 R8
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156 RETURNS: C++ EH Data registers (R3 - R6.)
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157
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158 We now set up R7/R8 and jump to rest_world_eh_r7r8.
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159
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160 rest_world doesn't use the R10 stack adjust parameter, nor does it
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161 pick up the R3-R6 exception handling stuff. */
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162
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163 .private_extern rest_world
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164 rest_world:
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165 /* Pickup previous SP */
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166 lwz r11, 0(r1)
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167 li r7, 0
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168 lwz r8, 8(r11)
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169 li r10, 0
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170 b rest_world_eh_r7r8
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171
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172 .private_extern eh_rest_world_r10
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173 eh_rest_world_r10:
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174 /* Pickup previous SP */
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175 lwz r11, 0(r1)
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176 mr r7,r10
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177 lwz r8, 8(r11)
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178 /* pickup the C++ EH data regs (R3 - R6.) */
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179 lwz r6,-420(r11)
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180 lwz r5,-424(r11)
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181 lwz r4,-428(r11)
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182 lwz r3,-432(r11)
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183
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184 b rest_world_eh_r7r8
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185
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186 /* rest_world_eh_r7r8 is jumped to -- not called! -- when we're doing
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187 the exception-handling epilog. R7 contains the offset to add to
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188 the SP, and R8 contains the 'real' return address.
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189
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190 USES: R0 R11 R12 [R7/R8]
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191 RETURNS: C++ EH Data registers (R3 - R6.) */
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192
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193 rest_world_eh_r7r8:
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194 bcl 20,31,Lr7r8$pb
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195 Lr7r8$pb: mflr r12
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196 lwz r11,0(r1)
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197 /* R11 := previous SP */
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198 addis r12,r12,ha16(L_has_vec$non_lazy_ptr-Lr7r8$pb)
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199 lwz r12,lo16(L_has_vec$non_lazy_ptr-Lr7r8$pb)(r12)
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200 lwz r0,4(r11)
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201 /* R0 := old CR */
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202 lwz r12,0(r12)
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203 /* R12 := HAS_VEC */
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204 mtcr r0
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205 cmpwi r12,0
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206 lmw r13,-220(r11)
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207 beq L.rest_world_fp_eh
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208 /* restore VRsave and V20..V31 */
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209 lwz r0,-224(r11)
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210 li r12,-416
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211 mtspr VRsave,r0
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212 lvx v20,r11,r12
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213 li r12,-400
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214 lvx v21,r11,r12
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215 li r12,-384
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216 lvx v22,r11,r12
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217 li r12,-368
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218 lvx v23,r11,r12
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219 li r12,-352
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220 lvx v24,r11,r12
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221 li r12,-336
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222 lvx v25,r11,r12
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223 li r12,-320
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224 lvx v26,r11,r12
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225 li r12,-304
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226 lvx v27,r11,r12
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227 li r12,-288
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228 lvx v28,r11,r12
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229 li r12,-272
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230 lvx v29,r11,r12
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231 li r12,-256
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232 lvx v30,r11,r12
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233 li r12,-240
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234 lvx v31,r11,r12
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235
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236 L.rest_world_fp_eh:
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237 lfd f14,-144(r11)
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238 lfd f15,-136(r11)
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239 lfd f16,-128(r11)
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240 lfd f17,-120(r11)
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241 lfd f18,-112(r11)
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242 lfd f19,-104(r11)
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243 lfd f20,-96(r11)
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244 lfd f21,-88(r11)
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245 lfd f22,-80(r11)
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246 lfd f23,-72(r11)
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247 lfd f24,-64(r11)
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248 lfd f25,-56(r11)
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249 lfd f26,-48(r11)
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250 lfd f27,-40(r11)
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251 lfd f28,-32(r11)
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252 lfd f29,-24(r11)
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253 lfd f30,-16(r11)
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254 /* R8 is the exception-handler's address */
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255 mtctr r8
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256 lfd f31,-8(r11)
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257 /* set SP to original value + R7 offset */
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258 add r1,r11,r7
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259 bctr
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