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annotate gcc/config/arm/cortex-a5.md @ 90:99e7b6776dd1

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implemeted __rectype expression. add CbC-exanples/fact-rectype.s
author Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
date Sun, 25 Dec 2011 04:04:42 +0900
parents 561a7518be6b
children 04ced10e8804
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68
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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1 ;; ARM Cortex-A5 pipeline description
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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2 ;; Copyright (C) 2010 Free Software Foundation, Inc.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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3 ;; Contributed by CodeSourcery.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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4 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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5 ;; This file is part of GCC.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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6 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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7 ;; GCC is free software; you can redistribute it and/or modify it
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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8 ;; under the terms of the GNU General Public License as published by
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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10 ;; any later version.
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11 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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15 ;; General Public License for more details.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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16 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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17 ;; You should have received a copy of the GNU General Public License
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "cortex_a5")
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22
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23 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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24 ;; Functional units.
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25 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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26
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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27 ;; The integer (ALU) pipeline. There are five DPU pipeline
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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28 ;; stages. However the decode/issue stages operate the same for all
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29 ;; instructions, so do not model them. We only need to model the
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30 ;; first execute stage because instructions always advance one stage
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31 ;; per cycle in order. Only branch instructions may dual-issue, so a
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32 ;; single unit covers all of the LS, ALU, MAC and FPU pipelines.
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33
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34 (define_cpu_unit "cortex_a5_ex1" "cortex_a5")
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35
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36 ;; The branch pipeline. Branches can dual-issue with other instructions
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37 ;; (except when those instructions take multiple cycles to issue).
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38
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39 (define_cpu_unit "cortex_a5_branch" "cortex_a5")
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40
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41 ;; Pseudo-unit for blocking the multiply pipeline when a double-precision
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42 ;; multiply is in progress.
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43
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44 (define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5")
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45
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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46 ;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
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47 ;; of the add pipeline by fmac instructions, etc.
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48
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49 (define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5")
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50
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51 ;; Floating-point div/sqrt (long latency, out-of-order completion).
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52
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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53 (define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5")
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54
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55 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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56 ;; ALU instructions.
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57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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58
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59 (define_insn_reservation "cortex_a5_alu" 2
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60 (and (eq_attr "tune" "cortexa5")
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61 (eq_attr "type" "alu"))
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62 "cortex_a5_ex1")
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63
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64 (define_insn_reservation "cortex_a5_alu_shift" 2
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65 (and (eq_attr "tune" "cortexa5")
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66 (eq_attr "type" "alu_shift,alu_shift_reg"))
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67 "cortex_a5_ex1")
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68
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69 ;; Forwarding path for unshifted operands.
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70
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71 (define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
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72 "cortex_a5_alu")
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73
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74 (define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
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75 "cortex_a5_alu_shift"
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76 "arm_no_early_alu_shift_dep")
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77
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78 ;; The multiplier pipeline can forward results from wr stage only so
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79 ;; there's no need to specify bypasses).
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80
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81 (define_insn_reservation "cortex_a5_mul" 2
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82 (and (eq_attr "tune" "cortexa5")
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83 (eq_attr "type" "mult"))
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84 "cortex_a5_ex1")
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85
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86 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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87 ;; Load/store instructions.
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88 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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89
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90 ;; Address-generation happens in the issue stage, which is one stage behind
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91 ;; the ex1 stage (the first stage we care about for scheduling purposes). The
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92 ;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
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93
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94 (define_insn_reservation "cortex_a5_load1" 2
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95 (and (eq_attr "tune" "cortexa5")
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96 (eq_attr "type" "load_byte,load1"))
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97 "cortex_a5_ex1")
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98
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99 (define_insn_reservation "cortex_a5_store1" 0
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100 (and (eq_attr "tune" "cortexa5")
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101 (eq_attr "type" "store1"))
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102 "cortex_a5_ex1")
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103
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104 (define_insn_reservation "cortex_a5_load2" 3
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105 (and (eq_attr "tune" "cortexa5")
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106 (eq_attr "type" "load2"))
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107 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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108
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109 (define_insn_reservation "cortex_a5_store2" 0
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110 (and (eq_attr "tune" "cortexa5")
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111 (eq_attr "type" "store2"))
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112 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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113
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114 (define_insn_reservation "cortex_a5_load3" 4
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115 (and (eq_attr "tune" "cortexa5")
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116 (eq_attr "type" "load3"))
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117 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
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118 cortex_a5_ex1")
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119
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120 (define_insn_reservation "cortex_a5_store3" 0
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
121 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
122 (eq_attr "type" "store3"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
123 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
124 cortex_a5_ex1")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
125
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
126 (define_insn_reservation "cortex_a5_load4" 5
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
127 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
128 (eq_attr "type" "load3"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
129 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
130 cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
131
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
132 (define_insn_reservation "cortex_a5_store4" 0
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
133 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
134 (eq_attr "type" "store3"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
135 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
136 cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
137
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 ;; Branches.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
140 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
141
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 ;; Direct branches are the only instructions we can dual-issue (also IT and
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 ;; nop, but those aren't very interesting for scheduling). (The latency here
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 ;; is meant to represent when the branch actually takes place, but may not be
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 ;; entirely correct.)
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
146
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 (define_insn_reservation "cortex_a5_branch" 3
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
148 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 (eq_attr "type" "branch,call"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
150 "cortex_a5_branch")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
151
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 ;; Floating-point arithmetic.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
155
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 (define_insn_reservation "cortex_a5_fpalu" 4
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
157 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
158 (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 fcmps, fcmpd"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 "cortex_a5_ex1+cortex_a5_fpadd_pipe")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
161
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 ;; f1 to f3 (which I think reduces the latency by one cycle).
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
164
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 (define_insn_reservation "cortex_a5_fconst" 3
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 (eq_attr "type" "fconsts,fconstd"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 "cortex_a5_ex1+cortex_a5_fpadd_pipe")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
169
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 ;; We should try not to attempt to issue a single-precision multiplication in
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
171 ;; the middle of a double-precision multiplication operation (the usage of
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 ;; cortex_a5_fpmul_pipe).
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
173
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 (define_insn_reservation "cortex_a5_fpmuls" 4
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 (eq_attr "type" "fmuls"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
177 "cortex_a5_ex1+cortex_a5_fpmul_pipe")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
178
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 ;; For single-precision multiply-accumulate, the add (accumulate) is issued
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 ;; whilst the multiply is in F4. The multiply result can then be forwarded
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 ;; from F5 to F1. The issue unit is only used once (when we first start
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 ;; processing the instruction), but the usage of the FP add pipeline could
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 ;; block other instructions attempting to use it simultaneously. We try to
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 ;; avoid that using cortex_a5_fpadd_pipe.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
185
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 (define_insn_reservation "cortex_a5_fpmacs" 8
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
188 (eq_attr "type" "fmacs"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
190
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 ;; Non-multiply instructions can issue in the middle two instructions of a
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 ;; double-precision multiply. Note that it isn't entirely clear when a branch
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
193 ;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
194 ;; that for now though.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
195
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 (define_insn_reservation "cortex_a5_fpmuld" 7
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
198 (eq_attr "type" "fmuld"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
199 "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
200 cortex_a5_ex1+cortex_a5_fpmul_pipe")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
201
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
202 (define_insn_reservation "cortex_a5_fpmacd" 11
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
204 (eq_attr "type" "fmacd"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
206 cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
207
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 ;; Floating-point divide/square root instructions.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
210 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
211
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
212 ;; ??? Not sure if the 14 cycles taken for single-precision divide to complete
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 ;; includes the time taken for the special instruction used to collect the
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
214 ;; result to travel down the multiply pipeline, or not. Assuming so. (If
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
215 ;; that's wrong, the latency should be increased by a few cycles.)
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
216
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
217 ;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
218 ;; multiply pipeline to collect the divide/square-root result.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
219
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
220 (define_insn_reservation "cortex_a5_fdivs" 14
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
221 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
222 (eq_attr "type" "fdivs"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
223 "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
224
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
225 ;; ??? Similarly for fdivd.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
226
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
227 (define_insn_reservation "cortex_a5_fdivd" 29
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
228 (and (eq_attr "tune" "cortexa5")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
229 (eq_attr "type" "fdivd"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
230 "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
231
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
232 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
233 ;; VFP to/from core transfers.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
234 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
235
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
236 ;; FP loads take data from wr/rot/f3.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
237
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
238 ;; Core-to-VFP transfers use the multiply pipeline.
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
239
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
240 (define_insn_reservation "cortex_a5_r2f" 4
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 (and (eq_attr "tune" "cortexa5")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 (eq_attr "type" "r_2_f"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
243 "cortex_a5_ex1")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
244
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
245 (define_insn_reservation "cortex_a5_f2r" 2
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 (and (eq_attr "tune" "cortexa5")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 (eq_attr "type" "f_2_r"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
248 "cortex_a5_ex1")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
249
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 ;; VFP flag transfer.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
252 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
253
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
254 ;; ??? The flag forwarding from fmstat to the ex2 stage of the second
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
255 ;; instruction is not modeled at present.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
256
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
257 (define_insn_reservation "cortex_a5_f_flags" 4
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
258 (and (eq_attr "tune" "cortexa5")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
259 (eq_attr "type" "f_flag"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
260 "cortex_a5_ex1")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
261
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
262 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
263 ;; VFP load/store.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
264 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
265
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
266 (define_insn_reservation "cortex_a5_f_loads" 4
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
267 (and (eq_attr "tune" "cortexa5")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
268 (eq_attr "type" "f_loads"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
269 "cortex_a5_ex1")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
270
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
271 (define_insn_reservation "cortex_a5_f_loadd" 5
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
272 (and (eq_attr "tune" "cortexa5")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
273 (eq_attr "type" "f_loadd"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
274 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
275
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
276 (define_insn_reservation "cortex_a5_f_stores" 0
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
277 (and (eq_attr "tune" "cortexa5")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
278 (eq_attr "type" "f_stores"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
279 "cortex_a5_ex1")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
280
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
281 (define_insn_reservation "cortex_a5_f_stored" 0
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
282 (and (eq_attr "tune" "cortexa5")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
283 (eq_attr "type" "f_stored"))
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
284 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
285
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
286 ;; Load-to-use for floating-point values has a penalty of one cycle,
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
287 ;; i.e. a latency of two.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
288
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
289 (define_bypass 2 "cortex_a5_f_loads"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
291 cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 cortex_a5_f2r")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
293
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
294 (define_bypass 3 "cortex_a5_f_loadd"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
295 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
296 cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
297 cortex_a5_f2r")