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1 ;; Pentium Scheduling
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2 ;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>. */
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19 ;;
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20 ;; The Pentium is an in-order core with two integer pipelines.
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21
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22 ;; True for insns that behave like prefixed insns on the Pentium.
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23 (define_attr "pent_prefix" "false,true"
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24 (if_then_else (ior (eq_attr "prefix_0f" "1")
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25 (ior (eq_attr "prefix_data16" "1")
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26 (eq_attr "prefix_rep" "1")))
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27 (const_string "true")
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28 (const_string "false")))
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29
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30 ;; Categorize how an instruction slots.
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31
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32 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
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33 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
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34 ;; rules, because it results in noticeably better code on non-MMX Pentium
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35 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
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36 ;; common, so the scheduler usually has a non-prefixed insn to pair).
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37
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38 (define_attr "pent_pair" "uv,pu,pv,np"
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39 (cond [(eq_attr "imm_disp" "true")
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40 (const_string "np")
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41 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
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42 (and (eq_attr "type" "pop,push")
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43 (eq_attr "memory" "!both")))
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44 (if_then_else (eq_attr "pent_prefix" "true")
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45 (const_string "pu")
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46 (const_string "uv"))
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47 (eq_attr "type" "ibr")
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48 (const_string "pv")
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49 (and (eq_attr "type" "ishift")
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50 (match_operand 2 "const_int_operand" ""))
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51 (const_string "pu")
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52 (and (eq_attr "type" "rotate")
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53 (match_operand 2 "const1_operand" ""))
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54 (const_string "pu")
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55 (and (eq_attr "type" "ishift1")
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56 (match_operand 1 "const_int_operand" ""))
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57 (const_string "pu")
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58 (and (eq_attr "type" "rotate1")
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59 (match_operand 1 "const1_operand" ""))
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60 (const_string "pu")
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61 (and (eq_attr "type" "call")
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62 (match_operand 0 "constant_call_address_operand" ""))
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63 (const_string "pv")
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64 (and (eq_attr "type" "callv")
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65 (match_operand 1 "constant_call_address_operand" ""))
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66 (const_string "pv")
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67 ]
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68 (const_string "np")))
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69
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70 (define_automaton "pentium,pentium_fpu")
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71
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72 ;; Pentium do have U and V pipes. Instruction to both pipes
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73 ;; are always issued together, much like on VLIW.
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74 ;;
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75 ;; predecode
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76 ;; / \
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77 ;; decodeu decodev
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78 ;; / | |
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79 ;; fpu executeu executev
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80 ;; | | |
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81 ;; fpu retire retire
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82 ;; |
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83 ;; fpu
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84 ;; We add dummy "port" pipes allocated only first cycle of
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85 ;; instruction to specify this behavior.
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86
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87 (define_cpu_unit "pentium-portu,pentium-portv" "pentium")
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88 (define_cpu_unit "pentium-u,pentium-v" "pentium")
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89 (absence_set "pentium-portu" "pentium-u,pentium-v")
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90 (presence_set "pentium-portv" "pentium-portu")
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91
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92 ;; Floating point instructions can overlap with new issue of integer
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93 ;; instructions. We model only first cycle of FP pipeline, as it is
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94 ;; fully pipelined.
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95 (define_cpu_unit "pentium-fp" "pentium_fpu")
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96
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97 ;; There is non-pipelined multiplier unit used for complex operations.
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98 (define_cpu_unit "pentium-fmul" "pentium_fpu")
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99
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100 ;; Pentium preserves memory ordering, so when load-execute-store
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101 ;; instruction is executed together with other instruction loading
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102 ;; data, the execution of the other instruction is delayed to very
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103 ;; last cycle of first instruction, when data are bypassed.
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104 ;; We model this by allocating "memory" unit when store is pending
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105 ;; and using conflicting load units together.
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106
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107 (define_cpu_unit "pentium-memory" "pentium")
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108 (define_cpu_unit "pentium-load0" "pentium")
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109 (define_cpu_unit "pentium-load1" "pentium")
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110 (absence_set "pentium-load0,pentium-load1" "pentium-memory")
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111
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112 (define_reservation "pentium-load" "(pentium-load0 | pentium-load1)")
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113 (define_reservation "pentium-np" "(pentium-u + pentium-v)")
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114 (define_reservation "pentium-uv" "(pentium-u | pentium-v)")
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115 (define_reservation "pentium-portuv" "(pentium-portu | pentium-portv)")
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116 (define_reservation "pentium-firstu" "(pentium-u + pentium-portu)")
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117 (define_reservation "pentium-firstv" "(pentium-v + pentium-portuv)")
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118 (define_reservation "pentium-firstuv" "(pentium-uv + pentium-portuv)")
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119 (define_reservation "pentium-firstuload" "(pentium-load + pentium-firstu)")
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120 (define_reservation "pentium-firstvload" "(pentium-load + pentium-firstv)")
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121 (define_reservation "pentium-firstuvload" "(pentium-load + pentium-firstuv)
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122 | (pentium-firstv,pentium-v,
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123 (pentium-load+pentium-firstv))")
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124 (define_reservation "pentium-firstuboth" "(pentium-load + pentium-firstu
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125 + pentium-memory)")
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126 (define_reservation "pentium-firstvboth" "(pentium-load + pentium-firstv
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127 + pentium-memory)")
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128 (define_reservation "pentium-firstuvboth" "(pentium-load + pentium-firstuv
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129 + pentium-memory)
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130 | (pentium-firstv,pentium-v,
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131 (pentium-load+pentium-firstv))")
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132
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133 ;; Few common long latency instructions
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134 (define_insn_reservation "pent_mul" 11
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135 (and (eq_attr "cpu" "pentium")
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136 (eq_attr "type" "imul"))
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137 "pentium-np*11")
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138
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139 (define_insn_reservation "pent_str" 12
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140 (and (eq_attr "cpu" "pentium")
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141 (eq_attr "type" "str"))
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142 "pentium-np*12")
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143
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144 ;; Integer division and some other long latency instruction block all
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145 ;; units, including the FP pipe. There is no value in modeling the
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146 ;; latency of these instructions and not modeling the latency
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147 ;; decreases the size of the DFA.
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148 (define_insn_reservation "pent_block" 1
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149 (and (eq_attr "cpu" "pentium")
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150 (eq_attr "type" "idiv"))
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151 "pentium-np+pentium-fp")
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152
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153 ;; Moves usually have one cycle penalty, but there are exceptions.
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154 (define_insn_reservation "pent_fmov" 1
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155 (and (eq_attr "cpu" "pentium")
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156 (and (eq_attr "type" "fmov")
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157 (eq_attr "memory" "none,load")))
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158 "(pentium-fp+pentium-np)")
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159
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160 (define_insn_reservation "pent_fpmovxf" 3
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161 (and (eq_attr "cpu" "pentium")
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162 (and (eq_attr "type" "fmov")
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163 (and (eq_attr "memory" "load,store")
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164 (eq_attr "mode" "XF"))))
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165 "(pentium-fp+pentium-np)*3")
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166
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167 (define_insn_reservation "pent_fpstore" 2
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168 (and (eq_attr "cpu" "pentium")
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169 (and (eq_attr "type" "fmov")
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170 (ior (match_operand 1 "immediate_operand" "")
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171 (eq_attr "memory" "store"))))
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172 "(pentium-fp+pentium-np)*2")
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173
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174 (define_insn_reservation "pent_imov" 1
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175 (and (eq_attr "cpu" "pentium")
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176 (eq_attr "type" "imov"))
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177 "pentium-firstuv")
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178
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179 ;; Push and pop instructions have 1 cycle latency and special
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180 ;; hardware bypass allows them to be paired with other push,pop
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181 ;; and call instructions.
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182 (define_bypass 0 "pent_push,pent_pop" "pent_push,pent_pop,pent_call")
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183 (define_insn_reservation "pent_push" 1
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184 (and (eq_attr "cpu" "pentium")
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185 (and (eq_attr "type" "push")
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186 (eq_attr "memory" "store")))
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187 "pentium-firstuv")
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188
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189 (define_insn_reservation "pent_pop" 1
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190 (and (eq_attr "cpu" "pentium")
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191 (eq_attr "type" "pop,leave"))
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192 "pentium-firstuv")
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193
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194 ;; Call and branch instruction can execute in either pipe, but
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195 ;; they are only pairable when in the v pipe.
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196 (define_insn_reservation "pent_call" 10
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197 (and (eq_attr "cpu" "pentium")
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198 (eq_attr "type" "call,callv"))
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199 "pentium-firstv,pentium-v*9")
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200
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201 (define_insn_reservation "pent_branch" 1
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202 (and (eq_attr "cpu" "pentium")
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203 (eq_attr "type" "ibr"))
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204 "pentium-firstv")
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205
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206 ;; Floating point instruction dispatch in U pipe, but continue
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207 ;; in FP pipeline allowing other instructions to be executed.
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208 (define_insn_reservation "pent_fp" 3
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209 (and (eq_attr "cpu" "pentium")
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210 (eq_attr "type" "fop,fistp"))
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211 "(pentium-firstu+pentium-fp),nothing,nothing")
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212
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213 ;; First two cycles of fmul are not pipelined.
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214 (define_insn_reservation "pent_fmul" 3
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215 (and (eq_attr "cpu" "pentium")
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216 (eq_attr "type" "fmul"))
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217 "(pentium-firstuv+pentium-fp+pentium-fmul),pentium-fmul,nothing")
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218
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219 ;; Long latency FP instructions overlap with integer instructions,
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220 ;; but only last 2 cycles with FP ones.
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221 (define_insn_reservation "pent_fdiv" 39
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222 (and (eq_attr "cpu" "pentium")
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223 (eq_attr "type" "fdiv"))
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224 "(pentium-np+pentium-fp+pentium-fmul),
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225 (pentium-fp+pentium-fmul)*36,pentium-fmul*2")
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226
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227 (define_insn_reservation "pent_fpspc" 70
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228 (and (eq_attr "cpu" "pentium")
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229 (eq_attr "type" "fpspc"))
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230 "(pentium-np+pentium-fp+pentium-fmul),
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231 (pentium-fp+pentium-fmul)*67,pentium-fmul*2")
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232
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233 ;; Integer instructions. Load/execute/store takes 3 cycles,
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234 ;; load/execute 2 cycles and execute only one cycle.
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235 (define_insn_reservation "pent_uv_both" 3
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236 (and (eq_attr "cpu" "pentium")
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237 (and (eq_attr "pent_pair" "uv")
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238 (eq_attr "memory" "both")))
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239 "pentium-firstuvboth,pentium-uv+pentium-memory,pentium-uv")
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240
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241 (define_insn_reservation "pent_u_both" 3
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242 (and (eq_attr "cpu" "pentium")
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243 (and (eq_attr "pent_pair" "pu")
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244 (eq_attr "memory" "both")))
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245 "pentium-firstuboth,pentium-u+pentium-memory,pentium-u")
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246
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247 (define_insn_reservation "pent_v_both" 3
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248 (and (eq_attr "cpu" "pentium")
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249 (and (eq_attr "pent_pair" "pv")
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250 (eq_attr "memory" "both")))
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251 "pentium-firstvboth,pentium-v+pentium-memory,pentium-v")
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252
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253 (define_insn_reservation "pent_np_both" 3
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254 (and (eq_attr "cpu" "pentium")
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255 (and (eq_attr "pent_pair" "np")
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256 (eq_attr "memory" "both")))
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257 "pentium-np,pentium-np,pentium-np")
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258
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259 (define_insn_reservation "pent_uv_load" 2
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260 (and (eq_attr "cpu" "pentium")
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261 (and (eq_attr "pent_pair" "uv")
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262 (eq_attr "memory" "load")))
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263 "pentium-firstuvload,pentium-uv")
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264
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265 (define_insn_reservation "pent_u_load" 2
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266 (and (eq_attr "cpu" "pentium")
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267 (and (eq_attr "pent_pair" "pu")
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268 (eq_attr "memory" "load")))
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269 "pentium-firstuload,pentium-u")
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270
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271 (define_insn_reservation "pent_v_load" 2
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272 (and (eq_attr "cpu" "pentium")
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273 (and (eq_attr "pent_pair" "pv")
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274 (eq_attr "memory" "load")))
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275 "pentium-firstvload,pentium-v")
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276
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277 (define_insn_reservation "pent_np_load" 2
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278 (and (eq_attr "cpu" "pentium")
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279 (and (eq_attr "pent_pair" "np")
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280 (eq_attr "memory" "load")))
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281 "pentium-np,pentium-np")
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282
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283 (define_insn_reservation "pent_uv" 1
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284 (and (eq_attr "cpu" "pentium")
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285 (and (eq_attr "pent_pair" "uv")
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286 (eq_attr "memory" "none")))
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287 "pentium-firstuv")
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288
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289 (define_insn_reservation "pent_u" 1
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290 (and (eq_attr "cpu" "pentium")
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291 (and (eq_attr "pent_pair" "pu")
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292 (eq_attr "memory" "none")))
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293 "pentium-firstu")
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294
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295 (define_insn_reservation "pent_v" 1
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296 (and (eq_attr "cpu" "pentium")
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297 (and (eq_attr "pent_pair" "pv")
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298 (eq_attr "memory" "none")))
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299 "pentium-firstv")
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300
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301 (define_insn_reservation "pent_np" 1
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302 (and (eq_attr "cpu" "pentium")
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303 (and (eq_attr "pent_pair" "np")
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304 (eq_attr "memory" "none")))
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305 "pentium-np")
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306
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