Mercurial > hg > CbC > CbC_gcc
annotate gcc/ira-costs.c @ 37:d096b2ff82d9
Added tag gcc.4.4.2 for changeset 855418dad1a3
| author | e075725 |
|---|---|
| date | Tue, 22 Dec 2009 21:52:56 +0900 |
| parents | 58ad6c70ea60 |
| children | 77e2b8dfacca |
| rev | line source |
|---|---|
| 0 | 1 /* IRA hard register and memory cost calculation for allocnos. |
| 2 Copyright (C) 2006, 2007, 2008 | |
| 3 Free Software Foundation, Inc. | |
| 4 Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify it under | |
| 9 the terms of the GNU General Public License as published by the Free | |
| 10 Software Foundation; either version 3, or (at your option) any later | |
| 11 version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 16 for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 #include "config.h" | |
| 23 #include "system.h" | |
| 24 #include "coretypes.h" | |
| 25 #include "tm.h" | |
| 26 #include "hard-reg-set.h" | |
| 27 #include "rtl.h" | |
| 28 #include "expr.h" | |
| 29 #include "tm_p.h" | |
| 30 #include "flags.h" | |
| 31 #include "basic-block.h" | |
| 32 #include "regs.h" | |
| 33 #include "addresses.h" | |
| 34 #include "insn-config.h" | |
| 35 #include "recog.h" | |
| 36 #include "toplev.h" | |
| 37 #include "target.h" | |
| 38 #include "params.h" | |
| 39 #include "ira-int.h" | |
| 40 | |
| 41 /* The file contains code is similar to one in regclass but the code | |
| 42 works on the allocno basis. */ | |
| 43 | |
| 44 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 45 /* Indexed by n, is TRUE if allocno with number N is used in an | |
| 46 auto-inc or auto-dec context. */ | |
| 47 static bool *in_inc_dec; | |
| 48 #endif | |
| 49 | |
| 50 /* The `costs' struct records the cost of using hard registers of each | |
| 51 class considered for the calculation and of using memory for each | |
| 52 allocno. */ | |
| 53 struct costs | |
| 54 { | |
| 55 int mem_cost; | |
| 56 /* Costs for register classes start here. We process only some | |
| 57 register classes (cover classes on the 1st cost calculation | |
| 58 iteration and important classes on the 2nd iteration). */ | |
| 59 int cost[1]; | |
| 60 }; | |
| 61 | |
| 62 /* Initialized once. It is a maximal possible size of the allocated | |
| 63 struct costs. */ | |
| 64 static int max_struct_costs_size; | |
| 65 | |
| 66 /* Allocated and initialized once, and used to initialize cost values | |
| 67 for each insn. */ | |
| 68 static struct costs *init_cost; | |
| 69 | |
| 70 /* Allocated once, and used for temporary purposes. */ | |
| 71 static struct costs *temp_costs; | |
| 72 | |
| 73 /* Allocated once, and used for the cost calculation. */ | |
| 74 static struct costs *op_costs[MAX_RECOG_OPERANDS]; | |
| 75 static struct costs *this_op_costs[MAX_RECOG_OPERANDS]; | |
| 76 | |
| 77 /* Original and accumulated costs of each class for each allocno. */ | |
| 78 static struct costs *allocno_costs, *total_costs; | |
| 79 | |
| 80 /* Classes used for cost calculation. They may be different on | |
| 81 different iterations of the cost calculations or in different | |
| 82 optimization modes. */ | |
| 83 static enum reg_class *cost_classes; | |
| 84 | |
| 85 /* The size of the previous array. */ | |
| 86 static int cost_classes_num; | |
| 87 | |
| 88 /* Map: cost class -> order number (they start with 0) of the cost | |
| 89 class. The order number is negative for non-cost classes. */ | |
| 90 static int cost_class_nums[N_REG_CLASSES]; | |
| 91 | |
| 92 /* It is the current size of struct costs. */ | |
| 93 static int struct_costs_size; | |
| 94 | |
| 95 /* Return pointer to structure containing costs of allocno with given | |
| 96 NUM in array ARR. */ | |
| 97 #define COSTS_OF_ALLOCNO(arr, num) \ | |
| 98 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size)) | |
| 99 | |
| 100 /* Record register class preferences of each allocno. Null value | |
| 101 means no preferences. It happens on the 1st iteration of the cost | |
| 102 calculation. */ | |
| 103 static enum reg_class *allocno_pref; | |
| 104 | |
| 105 /* Allocated buffers for allocno_pref. */ | |
| 106 static enum reg_class *allocno_pref_buffer; | |
| 107 | |
| 108 /* Record register class of each allocno with the same regno. */ | |
| 109 static enum reg_class *common_classes; | |
| 110 | |
| 111 /* Execution frequency of the current insn. */ | |
| 112 static int frequency; | |
| 113 | |
| 114 | |
| 115 | |
| 116 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if | |
| 117 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not | |
| 118 be a pseudo register. */ | |
| 119 static int | |
| 120 copy_cost (rtx x, enum machine_mode mode, enum reg_class rclass, bool to_p, | |
| 121 secondary_reload_info *prev_sri) | |
| 122 { | |
| 123 secondary_reload_info sri; | |
| 124 enum reg_class secondary_class = NO_REGS; | |
| 125 | |
| 126 /* If X is a SCRATCH, there is actually nothing to move since we are | |
| 127 assuming optimal allocation. */ | |
| 128 if (GET_CODE (x) == SCRATCH) | |
| 129 return 0; | |
| 130 | |
| 131 /* Get the class we will actually use for a reload. */ | |
| 132 rclass = PREFERRED_RELOAD_CLASS (x, rclass); | |
| 133 | |
| 134 /* If we need a secondary reload for an intermediate, the cost is | |
| 135 that to load the input into the intermediate register, then to | |
| 136 copy it. */ | |
| 137 sri.prev_sri = prev_sri; | |
| 138 sri.extra_cost = 0; | |
| 139 secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri); | |
| 140 | |
| 141 if (secondary_class != NO_REGS) | |
| 142 { | |
| 143 if (!move_cost[mode]) | |
| 144 init_move_cost (mode); | |
| 145 return (move_cost[mode][secondary_class][rclass] + sri.extra_cost | |
| 146 + copy_cost (x, mode, secondary_class, to_p, &sri)); | |
| 147 } | |
| 148 | |
| 149 /* For memory, use the memory move cost, for (hard) registers, use | |
| 150 the cost to move between the register classes, and use 2 for | |
| 151 everything else (constants). */ | |
| 152 if (MEM_P (x) || rclass == NO_REGS) | |
| 153 return sri.extra_cost + ira_memory_move_cost[mode][rclass][to_p != 0]; | |
| 154 else if (REG_P (x)) | |
| 155 { | |
| 156 if (!move_cost[mode]) | |
| 157 init_move_cost (mode); | |
| 158 return (sri.extra_cost + move_cost[mode][REGNO_REG_CLASS (REGNO (x))][rclass]); | |
| 159 } | |
| 160 else | |
| 161 /* If this is a constant, we may eventually want to call rtx_cost | |
| 162 here. */ | |
| 163 return sri.extra_cost + COSTS_N_INSNS (1); | |
| 164 } | |
| 165 | |
| 166 | |
| 167 | |
| 168 /* Record the cost of using memory or hard registers of various | |
| 169 classes for the operands in INSN. | |
| 170 | |
| 171 N_ALTS is the number of alternatives. | |
| 172 N_OPS is the number of operands. | |
| 173 OPS is an array of the operands. | |
| 174 MODES are the modes of the operands, in case any are VOIDmode. | |
| 175 CONSTRAINTS are the constraints to use for the operands. This array | |
| 176 is modified by this procedure. | |
| 177 | |
| 178 This procedure works alternative by alternative. For each | |
| 179 alternative we assume that we will be able to allocate all allocnos | |
| 180 to their ideal register class and calculate the cost of using that | |
| 181 alternative. Then we compute, for each operand that is a | |
| 182 pseudo-register, the cost of having the allocno allocated to each | |
| 183 register class and using it in that alternative. To this cost is | |
| 184 added the cost of the alternative. | |
| 185 | |
| 186 The cost of each class for this insn is its lowest cost among all | |
| 187 the alternatives. */ | |
| 188 static void | |
| 189 record_reg_classes (int n_alts, int n_ops, rtx *ops, | |
| 190 enum machine_mode *modes, const char **constraints, | |
| 191 rtx insn, struct costs **op_costs, | |
| 192 enum reg_class *allocno_pref) | |
| 193 { | |
| 194 int alt; | |
| 195 int i, j, k; | |
| 196 rtx set; | |
| 197 int insn_allows_mem[MAX_RECOG_OPERANDS]; | |
| 198 | |
| 199 for (i = 0; i < n_ops; i++) | |
| 200 insn_allows_mem[i] = 0; | |
| 201 | |
| 202 /* Process each alternative, each time minimizing an operand's cost | |
| 203 with the cost for each operand in that alternative. */ | |
| 204 for (alt = 0; alt < n_alts; alt++) | |
| 205 { | |
| 206 enum reg_class classes[MAX_RECOG_OPERANDS]; | |
| 207 int allows_mem[MAX_RECOG_OPERANDS]; | |
| 208 int rclass; | |
| 209 int alt_fail = 0; | |
| 210 int alt_cost = 0, op_cost_add; | |
| 211 | |
| 212 for (i = 0; i < n_ops; i++) | |
| 213 { | |
| 214 unsigned char c; | |
| 215 const char *p = constraints[i]; | |
| 216 rtx op = ops[i]; | |
| 217 enum machine_mode mode = modes[i]; | |
| 218 int allows_addr = 0; | |
| 219 int win = 0; | |
| 220 | |
| 221 /* Initially show we know nothing about the register class. */ | |
| 222 classes[i] = NO_REGS; | |
| 223 allows_mem[i] = 0; | |
| 224 | |
| 225 /* If this operand has no constraints at all, we can | |
| 226 conclude nothing about it since anything is valid. */ | |
| 227 if (*p == 0) | |
| 228 { | |
| 229 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
| 230 memset (this_op_costs[i], 0, struct_costs_size); | |
| 231 continue; | |
| 232 } | |
| 233 | |
| 234 /* If this alternative is only relevant when this operand | |
| 235 matches a previous operand, we do different things | |
| 236 depending on whether this operand is a allocno-reg or not. | |
| 237 We must process any modifiers for the operand before we | |
| 238 can make this test. */ | |
| 239 while (*p == '%' || *p == '=' || *p == '+' || *p == '&') | |
| 240 p++; | |
| 241 | |
| 242 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) | |
| 243 { | |
| 244 /* Copy class and whether memory is allowed from the | |
| 245 matching alternative. Then perform any needed cost | |
| 246 computations and/or adjustments. */ | |
| 247 j = p[0] - '0'; | |
| 248 classes[i] = classes[j]; | |
| 249 allows_mem[i] = allows_mem[j]; | |
| 250 if (allows_mem[i]) | |
| 251 insn_allows_mem[i] = 1; | |
| 252 | |
| 253 if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
| 254 { | |
| 255 /* If this matches the other operand, we have no | |
| 256 added cost and we win. */ | |
| 257 if (rtx_equal_p (ops[j], op)) | |
| 258 win = 1; | |
| 259 /* If we can put the other operand into a register, | |
| 260 add to the cost of this alternative the cost to | |
| 261 copy this operand to the register used for the | |
| 262 other operand. */ | |
| 263 else if (classes[j] != NO_REGS) | |
| 264 { | |
| 265 alt_cost += copy_cost (op, mode, classes[j], 1, NULL); | |
| 266 win = 1; | |
| 267 } | |
| 268 } | |
| 269 else if (! REG_P (ops[j]) | |
| 270 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
| 271 { | |
| 272 /* This op is an allocno but the one it matches is | |
| 273 not. */ | |
| 274 | |
| 275 /* If we can't put the other operand into a | |
| 276 register, this alternative can't be used. */ | |
| 277 | |
| 278 if (classes[j] == NO_REGS) | |
| 279 alt_fail = 1; | |
| 280 /* Otherwise, add to the cost of this alternative | |
| 281 the cost to copy the other operand to the hard | |
| 282 register used for this operand. */ | |
| 283 else | |
| 284 alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL); | |
| 285 } | |
| 286 else | |
| 287 { | |
| 288 /* The costs of this operand are not the same as the | |
| 289 other operand since move costs are not symmetric. | |
| 290 Moreover, if we cannot tie them, this alternative | |
| 291 needs to do a copy, which is one insn. */ | |
| 292 struct costs *pp = this_op_costs[i]; | |
| 293 | |
| 294 for (k = 0; k < cost_classes_num; k++) | |
| 295 { | |
| 296 rclass = cost_classes[k]; | |
| 297 pp->cost[k] | |
|
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298 = (((recog_data.operand_type[i] != OP_OUT |
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299 ? ira_get_may_move_cost (mode, rclass, |
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300 classes[i], true) : 0) |
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301 + (recog_data.operand_type[i] != OP_IN |
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302 ? ira_get_may_move_cost (mode, classes[i], |
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303 rclass, false) : 0)) |
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304 * frequency); |
| 0 | 305 } |
| 306 | |
| 307 /* If the alternative actually allows memory, make | |
| 308 things a bit cheaper since we won't need an extra | |
| 309 insn to load it. */ | |
| 310 pp->mem_cost | |
| 311 = ((recog_data.operand_type[i] != OP_IN | |
| 312 ? ira_memory_move_cost[mode][classes[i]][0] : 0) | |
| 313 + (recog_data.operand_type[i] != OP_OUT | |
| 314 ? ira_memory_move_cost[mode][classes[i]][1] : 0) | |
| 315 - allows_mem[i]) * frequency; | |
| 316 | |
| 317 /* If we have assigned a class to this allocno in our | |
| 318 first pass, add a cost to this alternative | |
| 319 corresponding to what we would add if this allocno | |
| 320 were not in the appropriate class. We could use | |
| 321 cover class here but it is less accurate | |
| 322 approximation. */ | |
| 323 if (allocno_pref) | |
| 324 { | |
| 325 enum reg_class pref_class | |
| 326 = allocno_pref[ALLOCNO_NUM | |
| 327 (ira_curr_regno_allocno_map | |
| 328 [REGNO (op)])]; | |
| 329 | |
| 330 if (pref_class == NO_REGS) | |
| 331 alt_cost | |
| 332 += ((recog_data.operand_type[i] != OP_IN | |
| 333 ? ira_memory_move_cost[mode][classes[i]][0] | |
| 334 : 0) | |
| 335 + (recog_data.operand_type[i] != OP_OUT | |
| 336 ? ira_memory_move_cost[mode][classes[i]][1] | |
| 337 : 0)); | |
| 338 else if (ira_reg_class_intersect | |
| 339 [pref_class][classes[i]] == NO_REGS) | |
|
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340 alt_cost += ira_get_register_move_cost (mode, |
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341 pref_class, |
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342 classes[i]); |
| 0 | 343 } |
| 344 if (REGNO (ops[i]) != REGNO (ops[j]) | |
| 345 && ! find_reg_note (insn, REG_DEAD, op)) | |
| 346 alt_cost += 2; | |
| 347 | |
| 348 /* This is in place of ordinary cost computation for | |
| 349 this operand, so skip to the end of the | |
| 350 alternative (should be just one character). */ | |
| 351 while (*p && *p++ != ',') | |
| 352 ; | |
| 353 | |
| 354 constraints[i] = p; | |
| 355 continue; | |
| 356 } | |
| 357 } | |
| 358 | |
| 359 /* Scan all the constraint letters. See if the operand | |
| 360 matches any of the constraints. Collect the valid | |
| 361 register classes and see if this operand accepts | |
| 362 memory. */ | |
| 363 while ((c = *p)) | |
| 364 { | |
| 365 switch (c) | |
| 366 { | |
| 367 case ',': | |
| 368 break; | |
| 369 case '*': | |
| 370 /* Ignore the next letter for this pass. */ | |
| 371 c = *++p; | |
| 372 break; | |
| 373 | |
| 374 case '?': | |
| 375 alt_cost += 2; | |
| 376 case '!': case '#': case '&': | |
| 377 case '0': case '1': case '2': case '3': case '4': | |
| 378 case '5': case '6': case '7': case '8': case '9': | |
| 379 break; | |
| 380 | |
| 381 case 'p': | |
| 382 allows_addr = 1; | |
| 383 win = address_operand (op, GET_MODE (op)); | |
| 384 /* We know this operand is an address, so we want it | |
| 385 to be allocated to a register that can be the | |
| 386 base of an address, i.e. BASE_REG_CLASS. */ | |
| 387 classes[i] | |
| 388 = ira_reg_class_union[classes[i]] | |
| 389 [base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; | |
| 390 break; | |
| 391 | |
| 392 case 'm': case 'o': case 'V': | |
| 393 /* It doesn't seem worth distinguishing between | |
| 394 offsettable and non-offsettable addresses | |
| 395 here. */ | |
| 396 insn_allows_mem[i] = allows_mem[i] = 1; | |
| 397 if (MEM_P (op)) | |
| 398 win = 1; | |
| 399 break; | |
| 400 | |
| 401 case '<': | |
| 402 if (MEM_P (op) | |
| 403 && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
| 404 || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
| 405 win = 1; | |
| 406 break; | |
| 407 | |
| 408 case '>': | |
| 409 if (MEM_P (op) | |
| 410 && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
| 411 || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
| 412 win = 1; | |
| 413 break; | |
| 414 | |
| 415 case 'E': | |
| 416 case 'F': | |
| 417 if (GET_CODE (op) == CONST_DOUBLE | |
| 418 || (GET_CODE (op) == CONST_VECTOR | |
| 419 && (GET_MODE_CLASS (GET_MODE (op)) | |
| 420 == MODE_VECTOR_FLOAT))) | |
| 421 win = 1; | |
| 422 break; | |
| 423 | |
| 424 case 'G': | |
| 425 case 'H': | |
| 426 if (GET_CODE (op) == CONST_DOUBLE | |
| 427 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) | |
| 428 win = 1; | |
| 429 break; | |
| 430 | |
| 431 case 's': | |
| 432 if (GET_CODE (op) == CONST_INT | |
| 433 || (GET_CODE (op) == CONST_DOUBLE | |
| 434 && GET_MODE (op) == VOIDmode)) | |
| 435 break; | |
| 436 | |
| 437 case 'i': | |
| 438 if (CONSTANT_P (op) | |
| 439 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))) | |
| 440 win = 1; | |
| 441 break; | |
| 442 | |
| 443 case 'n': | |
| 444 if (GET_CODE (op) == CONST_INT | |
| 445 || (GET_CODE (op) == CONST_DOUBLE | |
| 446 && GET_MODE (op) == VOIDmode)) | |
| 447 win = 1; | |
| 448 break; | |
| 449 | |
| 450 case 'I': | |
| 451 case 'J': | |
| 452 case 'K': | |
| 453 case 'L': | |
| 454 case 'M': | |
| 455 case 'N': | |
| 456 case 'O': | |
| 457 case 'P': | |
| 458 if (GET_CODE (op) == CONST_INT | |
| 459 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) | |
| 460 win = 1; | |
| 461 break; | |
| 462 | |
| 463 case 'X': | |
| 464 win = 1; | |
| 465 break; | |
| 466 | |
| 467 case 'g': | |
| 468 if (MEM_P (op) | |
| 469 || (CONSTANT_P (op) | |
| 470 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) | |
| 471 win = 1; | |
| 472 insn_allows_mem[i] = allows_mem[i] = 1; | |
| 473 case 'r': | |
| 474 classes[i] = ira_reg_class_union[classes[i]][GENERAL_REGS]; | |
| 475 break; | |
| 476 | |
| 477 default: | |
| 478 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) | |
| 479 classes[i] = ira_reg_class_union[classes[i]] | |
| 480 [REG_CLASS_FROM_CONSTRAINT (c, p)]; | |
| 481 #ifdef EXTRA_CONSTRAINT_STR | |
| 482 else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
| 483 win = 1; | |
| 484 | |
| 485 if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
| 486 { | |
| 487 /* Every MEM can be reloaded to fit. */ | |
| 488 insn_allows_mem[i] = allows_mem[i] = 1; | |
| 489 if (MEM_P (op)) | |
| 490 win = 1; | |
| 491 } | |
| 492 if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
| 493 { | |
| 494 /* Every address can be reloaded to fit. */ | |
| 495 allows_addr = 1; | |
| 496 if (address_operand (op, GET_MODE (op))) | |
| 497 win = 1; | |
| 498 /* We know this operand is an address, so we | |
| 499 want it to be allocated to a hard register | |
| 500 that can be the base of an address, | |
| 501 i.e. BASE_REG_CLASS. */ | |
| 502 classes[i] | |
| 503 = ira_reg_class_union[classes[i]] | |
| 504 [base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; | |
| 505 } | |
| 506 #endif | |
| 507 break; | |
| 508 } | |
| 509 p += CONSTRAINT_LEN (c, p); | |
| 510 if (c == ',') | |
| 511 break; | |
| 512 } | |
| 513 | |
| 514 constraints[i] = p; | |
| 515 | |
| 516 /* How we account for this operand now depends on whether it | |
| 517 is a pseudo register or not. If it is, we first check if | |
| 518 any register classes are valid. If not, we ignore this | |
| 519 alternative, since we want to assume that all allocnos get | |
| 520 allocated for register preferencing. If some register | |
| 521 class is valid, compute the costs of moving the allocno | |
| 522 into that class. */ | |
| 523 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
| 524 { | |
| 525 if (classes[i] == NO_REGS) | |
| 526 { | |
| 527 /* We must always fail if the operand is a REG, but | |
| 528 we did not find a suitable class. | |
| 529 | |
| 530 Otherwise we may perform an uninitialized read | |
| 531 from this_op_costs after the `continue' statement | |
| 532 below. */ | |
| 533 alt_fail = 1; | |
| 534 } | |
| 535 else | |
| 536 { | |
| 537 struct costs *pp = this_op_costs[i]; | |
| 538 | |
| 539 for (k = 0; k < cost_classes_num; k++) | |
| 540 { | |
| 541 rclass = cost_classes[k]; | |
| 542 pp->cost[k] | |
|
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543 = (((recog_data.operand_type[i] != OP_OUT |
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544 ? ira_get_may_move_cost (mode, rclass, |
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545 classes[i], true) : 0) |
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546 + (recog_data.operand_type[i] != OP_IN |
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547 ? ira_get_may_move_cost (mode, classes[i], |
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548 rclass, false) : 0)) |
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549 * frequency); |
| 0 | 550 } |
| 551 | |
| 552 /* If the alternative actually allows memory, make | |
| 553 things a bit cheaper since we won't need an extra | |
| 554 insn to load it. */ | |
| 555 pp->mem_cost | |
| 556 = ((recog_data.operand_type[i] != OP_IN | |
| 557 ? ira_memory_move_cost[mode][classes[i]][0] : 0) | |
| 558 + (recog_data.operand_type[i] != OP_OUT | |
| 559 ? ira_memory_move_cost[mode][classes[i]][1] : 0) | |
| 560 - allows_mem[i]) * frequency; | |
| 561 /* If we have assigned a class to this allocno in our | |
| 562 first pass, add a cost to this alternative | |
| 563 corresponding to what we would add if this allocno | |
| 564 were not in the appropriate class. We could use | |
| 565 cover class here but it is less accurate | |
| 566 approximation. */ | |
| 567 if (allocno_pref) | |
| 568 { | |
| 569 enum reg_class pref_class | |
| 570 = allocno_pref[ALLOCNO_NUM | |
| 571 (ira_curr_regno_allocno_map | |
| 572 [REGNO (op)])]; | |
| 573 | |
| 574 if (pref_class == NO_REGS) | |
| 575 alt_cost | |
| 576 += ((recog_data.operand_type[i] != OP_IN | |
| 577 ? ira_memory_move_cost[mode][classes[i]][0] | |
| 578 : 0) | |
| 579 + (recog_data.operand_type[i] != OP_OUT | |
| 580 ? ira_memory_move_cost[mode][classes[i]][1] | |
| 581 : 0)); | |
| 582 else if (ira_reg_class_intersect[pref_class][classes[i]] | |
| 583 == NO_REGS) | |
|
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584 alt_cost += ira_get_register_move_cost (mode, |
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585 pref_class, |
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586 classes[i]); |
| 0 | 587 } |
| 588 } | |
| 589 } | |
| 590 | |
| 591 /* Otherwise, if this alternative wins, either because we | |
| 592 have already determined that or if we have a hard | |
| 593 register of the proper class, there is no cost for this | |
| 594 alternative. */ | |
| 595 else if (win || (REG_P (op) | |
| 596 && reg_fits_class_p (op, classes[i], | |
| 597 0, GET_MODE (op)))) | |
| 598 ; | |
| 599 | |
| 600 /* If registers are valid, the cost of this alternative | |
| 601 includes copying the object to and/or from a | |
| 602 register. */ | |
| 603 else if (classes[i] != NO_REGS) | |
| 604 { | |
| 605 if (recog_data.operand_type[i] != OP_OUT) | |
| 606 alt_cost += copy_cost (op, mode, classes[i], 1, NULL); | |
| 607 | |
| 608 if (recog_data.operand_type[i] != OP_IN) | |
| 609 alt_cost += copy_cost (op, mode, classes[i], 0, NULL); | |
| 610 } | |
| 611 /* The only other way this alternative can be used is if | |
| 612 this is a constant that could be placed into memory. */ | |
| 613 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) | |
| 614 alt_cost += ira_memory_move_cost[mode][classes[i]][1]; | |
| 615 else | |
| 616 alt_fail = 1; | |
| 617 } | |
| 618 | |
| 619 if (alt_fail) | |
| 620 continue; | |
| 621 | |
| 622 op_cost_add = alt_cost * frequency; | |
| 623 /* Finally, update the costs with the information we've | |
| 624 calculated about this alternative. */ | |
| 625 for (i = 0; i < n_ops; i++) | |
| 626 if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
| 627 { | |
| 628 struct costs *pp = op_costs[i], *qq = this_op_costs[i]; | |
| 629 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); | |
| 630 | |
| 631 pp->mem_cost = MIN (pp->mem_cost, | |
| 632 (qq->mem_cost + op_cost_add) * scale); | |
| 633 | |
| 634 for (k = 0; k < cost_classes_num; k++) | |
| 635 pp->cost[k] | |
| 636 = MIN (pp->cost[k], (qq->cost[k] + op_cost_add) * scale); | |
| 637 } | |
| 638 } | |
| 639 | |
| 640 for (i = 0; i < n_ops; i++) | |
| 641 { | |
| 642 ira_allocno_t a; | |
| 643 rtx op = ops[i]; | |
| 644 | |
| 645 if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
| 646 continue; | |
| 647 a = ira_curr_regno_allocno_map [REGNO (op)]; | |
| 648 if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0) | |
| 649 ALLOCNO_BAD_SPILL_P (a) = true; | |
| 650 } | |
| 651 | |
| 652 /* If this insn is a single set copying operand 1 to operand 0 and | |
| 653 one operand is an allocno with the other a hard reg or an allocno | |
| 654 that prefers a hard register that is in its own register class | |
| 655 then we may want to adjust the cost of that register class to -1. | |
| 656 | |
| 657 Avoid the adjustment if the source does not die to avoid | |
| 658 stressing of register allocator by preferrencing two colliding | |
| 659 registers into single class. | |
| 660 | |
| 661 Also avoid the adjustment if a copy between hard registers of the | |
| 662 class is expensive (ten times the cost of a default copy is | |
| 663 considered arbitrarily expensive). This avoids losing when the | |
| 664 preferred class is very expensive as the source of a copy | |
| 665 instruction. */ | |
| 666 if ((set = single_set (insn)) != 0 | |
| 667 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
| 668 && REG_P (ops[0]) && REG_P (ops[1]) | |
| 669 && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
| 670 for (i = 0; i <= 1; i++) | |
| 671 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
| 672 { | |
| 673 unsigned int regno = REGNO (ops[!i]); | |
| 674 enum machine_mode mode = GET_MODE (ops[!i]); | |
| 675 int rclass; | |
| 676 unsigned int nr; | |
| 677 | |
| 678 if (regno < FIRST_PSEUDO_REGISTER) | |
| 679 for (k = 0; k < cost_classes_num; k++) | |
| 680 { | |
| 681 rclass = cost_classes[k]; | |
| 682 if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno) | |
| 683 && (reg_class_size[rclass] | |
| 684 == (unsigned) CLASS_MAX_NREGS (rclass, mode))) | |
| 685 { | |
| 686 if (reg_class_size[rclass] == 1) | |
| 687 op_costs[i]->cost[k] = -frequency; | |
| 688 else | |
| 689 { | |
| 690 for (nr = 0; | |
| 691 nr < (unsigned) hard_regno_nregs[regno][mode]; | |
| 692 nr++) | |
| 693 if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], | |
| 694 regno + nr)) | |
| 695 break; | |
| 696 | |
| 697 if (nr == (unsigned) hard_regno_nregs[regno][mode]) | |
| 698 op_costs[i]->cost[k] = -frequency; | |
| 699 } | |
| 700 } | |
| 701 } | |
| 702 } | |
| 703 } | |
| 704 | |
| 705 | |
| 706 | |
| 707 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */ | |
| 708 static inline bool | |
| 709 ok_for_index_p_nonstrict (rtx reg) | |
| 710 { | |
| 711 unsigned regno = REGNO (reg); | |
| 712 | |
| 713 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); | |
| 714 } | |
| 715 | |
| 716 /* A version of regno_ok_for_base_p for use here, when all | |
| 717 pseudo-registers should count as OK. Arguments as for | |
| 718 regno_ok_for_base_p. */ | |
| 719 static inline bool | |
| 720 ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode, | |
| 721 enum rtx_code outer_code, enum rtx_code index_code) | |
| 722 { | |
| 723 unsigned regno = REGNO (reg); | |
| 724 | |
| 725 if (regno >= FIRST_PSEUDO_REGISTER) | |
| 726 return true; | |
| 727 return ok_for_base_p_1 (regno, mode, outer_code, index_code); | |
| 728 } | |
| 729 | |
| 730 /* Record the pseudo registers we must reload into hard registers in a | |
| 731 subexpression of a memory address, X. | |
| 732 | |
| 733 If CONTEXT is 0, we are looking at the base part of an address, | |
| 734 otherwise we are looking at the index part. | |
| 735 | |
| 736 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE | |
| 737 give the context that the rtx appears in. These three arguments | |
| 738 are passed down to base_reg_class. | |
| 739 | |
| 740 SCALE is twice the amount to multiply the cost by (it is twice so | |
| 741 we can represent half-cost adjustments). */ | |
| 742 static void | |
| 743 record_address_regs (enum machine_mode mode, rtx x, int context, | |
| 744 enum rtx_code outer_code, enum rtx_code index_code, | |
| 745 int scale) | |
| 746 { | |
| 747 enum rtx_code code = GET_CODE (x); | |
| 748 enum reg_class rclass; | |
| 749 | |
| 750 if (context == 1) | |
| 751 rclass = INDEX_REG_CLASS; | |
| 752 else | |
| 753 rclass = base_reg_class (mode, outer_code, index_code); | |
| 754 | |
| 755 switch (code) | |
| 756 { | |
| 757 case CONST_INT: | |
| 758 case CONST: | |
| 759 case CC0: | |
| 760 case PC: | |
| 761 case SYMBOL_REF: | |
| 762 case LABEL_REF: | |
| 763 return; | |
| 764 | |
| 765 case PLUS: | |
| 766 /* When we have an address that is a sum, we must determine | |
| 767 whether registers are "base" or "index" regs. If there is a | |
| 768 sum of two registers, we must choose one to be the "base". | |
| 769 Luckily, we can use the REG_POINTER to make a good choice | |
| 770 most of the time. We only need to do this on machines that | |
| 771 can have two registers in an address and where the base and | |
| 772 index register classes are different. | |
| 773 | |
| 774 ??? This code used to set REGNO_POINTER_FLAG in some cases, | |
| 775 but that seems bogus since it should only be set when we are | |
| 776 sure the register is being used as a pointer. */ | |
| 777 { | |
| 778 rtx arg0 = XEXP (x, 0); | |
| 779 rtx arg1 = XEXP (x, 1); | |
| 780 enum rtx_code code0 = GET_CODE (arg0); | |
| 781 enum rtx_code code1 = GET_CODE (arg1); | |
| 782 | |
| 783 /* Look inside subregs. */ | |
| 784 if (code0 == SUBREG) | |
| 785 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); | |
| 786 if (code1 == SUBREG) | |
| 787 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); | |
| 788 | |
| 789 /* If this machine only allows one register per address, it | |
| 790 must be in the first operand. */ | |
| 791 if (MAX_REGS_PER_ADDRESS == 1) | |
| 792 record_address_regs (mode, arg0, 0, PLUS, code1, scale); | |
| 793 | |
| 794 /* If index and base registers are the same on this machine, | |
| 795 just record registers in any non-constant operands. We | |
| 796 assume here, as well as in the tests below, that all | |
| 797 addresses are in canonical form. */ | |
| 798 else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH)) | |
| 799 { | |
| 800 record_address_regs (mode, arg0, context, PLUS, code1, scale); | |
| 801 if (! CONSTANT_P (arg1)) | |
| 802 record_address_regs (mode, arg1, context, PLUS, code0, scale); | |
| 803 } | |
| 804 | |
| 805 /* If the second operand is a constant integer, it doesn't | |
| 806 change what class the first operand must be. */ | |
| 807 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
| 808 record_address_regs (mode, arg0, context, PLUS, code1, scale); | |
| 809 /* If the second operand is a symbolic constant, the first | |
| 810 operand must be an index register. */ | |
| 811 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
| 812 record_address_regs (mode, arg0, 1, PLUS, code1, scale); | |
| 813 /* If both operands are registers but one is already a hard | |
| 814 register of index or reg-base class, give the other the | |
| 815 class that the hard register is not. */ | |
| 816 else if (code0 == REG && code1 == REG | |
| 817 && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
| 818 && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) | |
| 819 || ok_for_index_p_nonstrict (arg0))) | |
| 820 record_address_regs (mode, arg1, | |
| 821 ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) | |
| 822 ? 1 : 0, | |
| 823 PLUS, REG, scale); | |
| 824 else if (code0 == REG && code1 == REG | |
| 825 && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
| 826 && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) | |
| 827 || ok_for_index_p_nonstrict (arg1))) | |
| 828 record_address_regs (mode, arg0, | |
| 829 ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) | |
| 830 ? 1 : 0, | |
| 831 PLUS, REG, scale); | |
| 832 /* If one operand is known to be a pointer, it must be the | |
| 833 base with the other operand the index. Likewise if the | |
| 834 other operand is a MULT. */ | |
| 835 else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT) | |
| 836 { | |
| 837 record_address_regs (mode, arg0, 0, PLUS, code1, scale); | |
| 838 record_address_regs (mode, arg1, 1, PLUS, code0, scale); | |
| 839 } | |
| 840 else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT) | |
| 841 { | |
| 842 record_address_regs (mode, arg0, 1, PLUS, code1, scale); | |
| 843 record_address_regs (mode, arg1, 0, PLUS, code0, scale); | |
| 844 } | |
| 845 /* Otherwise, count equal chances that each might be a base or | |
| 846 index register. This case should be rare. */ | |
| 847 else | |
| 848 { | |
| 849 record_address_regs (mode, arg0, 0, PLUS, code1, scale / 2); | |
| 850 record_address_regs (mode, arg0, 1, PLUS, code1, scale / 2); | |
| 851 record_address_regs (mode, arg1, 0, PLUS, code0, scale / 2); | |
| 852 record_address_regs (mode, arg1, 1, PLUS, code0, scale / 2); | |
| 853 } | |
| 854 } | |
| 855 break; | |
| 856 | |
| 857 /* Double the importance of an allocno that is incremented or | |
| 858 decremented, since it would take two extra insns if it ends | |
| 859 up in the wrong place. */ | |
| 860 case POST_MODIFY: | |
| 861 case PRE_MODIFY: | |
| 862 record_address_regs (mode, XEXP (x, 0), 0, code, | |
| 863 GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale); | |
| 864 if (REG_P (XEXP (XEXP (x, 1), 1))) | |
| 865 record_address_regs (mode, XEXP (XEXP (x, 1), 1), 1, code, REG, | |
| 866 2 * scale); | |
| 867 break; | |
| 868 | |
| 869 case POST_INC: | |
| 870 case PRE_INC: | |
| 871 case POST_DEC: | |
| 872 case PRE_DEC: | |
| 873 /* Double the importance of an allocno that is incremented or | |
| 874 decremented, since it would take two extra insns if it ends | |
| 875 up in the wrong place. If the operand is a pseudo-register, | |
| 876 show it is being used in an INC_DEC context. */ | |
| 877 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 878 if (REG_P (XEXP (x, 0)) | |
| 879 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
| 880 in_inc_dec[ALLOCNO_NUM (ira_curr_regno_allocno_map | |
| 881 [REGNO (XEXP (x, 0))])] = true; | |
| 882 #endif | |
| 883 record_address_regs (mode, XEXP (x, 0), 0, code, SCRATCH, 2 * scale); | |
| 884 break; | |
| 885 | |
| 886 case REG: | |
| 887 { | |
| 888 struct costs *pp; | |
| 889 int i, k; | |
| 890 | |
| 891 if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
| 892 break; | |
| 893 | |
| 894 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[REGNO (x)]) = true; | |
| 895 pp = COSTS_OF_ALLOCNO (allocno_costs, | |
| 896 ALLOCNO_NUM (ira_curr_regno_allocno_map | |
| 897 [REGNO (x)])); | |
| 898 pp->mem_cost += (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2; | |
| 899 for (k = 0; k < cost_classes_num; k++) | |
| 900 { | |
| 901 i = cost_classes[k]; | |
| 902 pp->cost[k] | |
|
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903 += (ira_get_may_move_cost (Pmode, i, rclass, true) * scale) / 2; |
| 0 | 904 } |
| 905 } | |
| 906 break; | |
| 907 | |
| 908 default: | |
| 909 { | |
| 910 const char *fmt = GET_RTX_FORMAT (code); | |
| 911 int i; | |
| 912 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
| 913 if (fmt[i] == 'e') | |
| 914 record_address_regs (mode, XEXP (x, i), context, code, SCRATCH, | |
| 915 scale); | |
| 916 } | |
| 917 } | |
| 918 } | |
| 919 | |
| 920 | |
| 921 | |
| 922 /* Calculate the costs of insn operands. */ | |
| 923 static void | |
| 924 record_operand_costs (rtx insn, struct costs **op_costs, | |
| 925 enum reg_class *allocno_pref) | |
| 926 { | |
| 927 const char *constraints[MAX_RECOG_OPERANDS]; | |
| 928 enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
| 929 int i; | |
| 930 | |
| 931 for (i = 0; i < recog_data.n_operands; i++) | |
| 932 { | |
| 933 constraints[i] = recog_data.constraints[i]; | |
| 934 modes[i] = recog_data.operand_mode[i]; | |
| 935 } | |
| 936 | |
| 937 /* If we get here, we are set up to record the costs of all the | |
| 938 operands for this insn. Start by initializing the costs. Then | |
| 939 handle any address registers. Finally record the desired classes | |
| 940 for any allocnos, doing it twice if some pair of operands are | |
| 941 commutative. */ | |
| 942 for (i = 0; i < recog_data.n_operands; i++) | |
| 943 { | |
| 944 memcpy (op_costs[i], init_cost, struct_costs_size); | |
| 945 | |
| 946 if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
| 947 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); | |
| 948 | |
| 949 if (MEM_P (recog_data.operand[i])) | |
| 950 record_address_regs (GET_MODE (recog_data.operand[i]), | |
| 951 XEXP (recog_data.operand[i], 0), | |
| 952 0, MEM, SCRATCH, frequency * 2); | |
| 953 else if (constraints[i][0] == 'p' | |
| 954 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], | |
| 955 constraints[i])) | |
| 956 record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS, | |
| 957 SCRATCH, frequency * 2); | |
| 958 } | |
| 959 | |
| 960 /* Check for commutative in a separate loop so everything will have | |
| 961 been initialized. We must do this even if one operand is a | |
| 962 constant--see addsi3 in m68k.md. */ | |
| 963 for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
| 964 if (constraints[i][0] == '%') | |
| 965 { | |
| 966 const char *xconstraints[MAX_RECOG_OPERANDS]; | |
| 967 int j; | |
| 968 | |
| 969 /* Handle commutative operands by swapping the constraints. | |
| 970 We assume the modes are the same. */ | |
| 971 for (j = 0; j < recog_data.n_operands; j++) | |
| 972 xconstraints[j] = constraints[j]; | |
| 973 | |
| 974 xconstraints[i] = constraints[i+1]; | |
| 975 xconstraints[i+1] = constraints[i]; | |
| 976 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
| 977 recog_data.operand, modes, | |
| 978 xconstraints, insn, op_costs, allocno_pref); | |
| 979 } | |
| 980 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
| 981 recog_data.operand, modes, | |
| 982 constraints, insn, op_costs, allocno_pref); | |
| 983 } | |
| 984 | |
| 985 | |
| 986 | |
| 987 /* Process one insn INSN. Scan it and record each time it would save | |
| 988 code to put a certain allocnos in a certain class. Return the last | |
| 989 insn processed, so that the scan can be continued from there. */ | |
| 990 static rtx | |
| 991 scan_one_insn (rtx insn) | |
| 992 { | |
| 993 enum rtx_code pat_code; | |
| 994 rtx set, note; | |
| 995 int i, k; | |
| 996 | |
| 997 if (!INSN_P (insn)) | |
| 998 return insn; | |
| 999 | |
| 1000 pat_code = GET_CODE (PATTERN (insn)); | |
| 1001 if (pat_code == USE || pat_code == CLOBBER || pat_code == ASM_INPUT | |
| 1002 || pat_code == ADDR_VEC || pat_code == ADDR_DIFF_VEC) | |
| 1003 return insn; | |
| 1004 | |
| 1005 set = single_set (insn); | |
| 1006 extract_insn (insn); | |
| 1007 | |
| 1008 /* If this insn loads a parameter from its stack slot, then it | |
| 1009 represents a savings, rather than a cost, if the parameter is | |
| 1010 stored in memory. Record this fact. */ | |
| 1011 if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set)) | |
| 1012 && (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX | |
| 1013 && MEM_P (XEXP (note, 0))) | |
| 1014 { | |
| 1015 enum reg_class cl = GENERAL_REGS; | |
| 1016 rtx reg = SET_DEST (set); | |
| 1017 int num = ALLOCNO_NUM (ira_curr_regno_allocno_map[REGNO (reg)]); | |
| 1018 | |
| 1019 if (allocno_pref) | |
| 1020 cl = allocno_pref[num]; | |
| 1021 COSTS_OF_ALLOCNO (allocno_costs, num)->mem_cost | |
| 1022 -= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency; | |
| 1023 record_address_regs (GET_MODE (SET_SRC (set)), XEXP (SET_SRC (set), 0), | |
| 1024 0, MEM, SCRATCH, frequency * 2); | |
| 1025 } | |
| 1026 | |
| 1027 record_operand_costs (insn, op_costs, allocno_pref); | |
| 1028 | |
| 1029 /* Now add the cost for each operand to the total costs for its | |
| 1030 allocno. */ | |
| 1031 for (i = 0; i < recog_data.n_operands; i++) | |
| 1032 if (REG_P (recog_data.operand[i]) | |
| 1033 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
| 1034 { | |
| 1035 int regno = REGNO (recog_data.operand[i]); | |
| 1036 struct costs *p | |
| 1037 = COSTS_OF_ALLOCNO (allocno_costs, | |
| 1038 ALLOCNO_NUM (ira_curr_regno_allocno_map[regno])); | |
| 1039 struct costs *q = op_costs[i]; | |
| 1040 | |
| 1041 p->mem_cost += q->mem_cost; | |
| 1042 for (k = 0; k < cost_classes_num; k++) | |
| 1043 p->cost[k] += q->cost[k]; | |
| 1044 } | |
| 1045 | |
| 1046 return insn; | |
| 1047 } | |
| 1048 | |
| 1049 | |
| 1050 | |
| 1051 /* Print allocnos costs to file F. */ | |
| 1052 static void | |
| 1053 print_costs (FILE *f) | |
| 1054 { | |
| 1055 int k; | |
| 1056 ira_allocno_t a; | |
| 1057 ira_allocno_iterator ai; | |
| 1058 | |
| 1059 fprintf (f, "\n"); | |
| 1060 FOR_EACH_ALLOCNO (a, ai) | |
| 1061 { | |
| 1062 int i, rclass; | |
| 1063 basic_block bb; | |
| 1064 int regno = ALLOCNO_REGNO (a); | |
| 1065 | |
| 1066 i = ALLOCNO_NUM (a); | |
| 1067 fprintf (f, " a%d(r%d,", i, regno); | |
| 1068 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
| 1069 fprintf (f, "b%d", bb->index); | |
| 1070 else | |
| 1071 fprintf (f, "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop->num); | |
| 1072 fprintf (f, ") costs:"); | |
| 1073 for (k = 0; k < cost_classes_num; k++) | |
| 1074 { | |
| 1075 rclass = cost_classes[k]; | |
| 1076 if (contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (regno)] | |
| 1077 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1078 && (! in_inc_dec[i] || ! forbidden_inc_dec_class[rclass]) | |
| 1079 #endif | |
| 1080 #ifdef CANNOT_CHANGE_MODE_CLASS | |
| 1081 && ! invalid_mode_change_p (regno, (enum reg_class) rclass, | |
| 1082 PSEUDO_REGNO_MODE (regno)) | |
| 1083 #endif | |
| 1084 ) | |
| 1085 { | |
| 1086 fprintf (f, " %s:%d", reg_class_names[rclass], | |
| 1087 COSTS_OF_ALLOCNO (allocno_costs, i)->cost[k]); | |
| 1088 if (flag_ira_region == IRA_REGION_ALL | |
| 1089 || flag_ira_region == IRA_REGION_MIXED) | |
| 1090 fprintf (f, ",%d", COSTS_OF_ALLOCNO (total_costs, i)->cost[k]); | |
| 1091 } | |
| 1092 } | |
| 1093 fprintf (f, " MEM:%i\n", COSTS_OF_ALLOCNO (allocno_costs, i)->mem_cost); | |
| 1094 } | |
| 1095 } | |
| 1096 | |
| 1097 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno | |
| 1098 costs. */ | |
| 1099 static void | |
| 1100 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node) | |
| 1101 { | |
| 1102 basic_block bb; | |
| 1103 rtx insn; | |
| 1104 | |
| 1105 bb = loop_tree_node->bb; | |
| 1106 if (bb == NULL) | |
| 1107 return; | |
| 1108 frequency = REG_FREQ_FROM_BB (bb); | |
| 1109 if (frequency == 0) | |
| 1110 frequency = 1; | |
| 1111 FOR_BB_INSNS (bb, insn) | |
| 1112 insn = scan_one_insn (insn); | |
| 1113 } | |
| 1114 | |
| 1115 /* Find costs of register classes and memory for allocnos and their | |
| 1116 best costs. */ | |
| 1117 static void | |
| 1118 find_allocno_class_costs (void) | |
| 1119 { | |
| 1120 int i, k; | |
| 1121 int pass; | |
| 1122 basic_block bb; | |
| 1123 | |
| 1124 init_recog (); | |
| 1125 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1126 in_inc_dec = ira_allocate (sizeof (bool) * ira_allocnos_num); | |
| 1127 #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
| 1128 allocno_pref = NULL; | |
| 1129 /* Normally we scan the insns once and determine the best class to | |
| 1130 use for each allocno. However, if -fexpensive-optimizations are | |
| 1131 on, we do so twice, the second time using the tentative best | |
| 1132 classes to guide the selection. */ | |
| 1133 for (pass = 0; pass <= flag_expensive_optimizations; pass++) | |
| 1134 { | |
| 1135 if (internal_flag_ira_verbose > 0 && ira_dump_file) | |
| 1136 fprintf (ira_dump_file, "\nPass %i for finding allocno costs\n\n", | |
| 1137 pass); | |
| 1138 /* We could use only cover classes. Unfortunately it does not | |
| 1139 work well for some targets where some subclass of cover class | |
| 1140 is costly and wrong cover class is chosen. */ | |
| 1141 for (i = 0; i < N_REG_CLASSES; i++) | |
| 1142 cost_class_nums[i] = -1; | |
| 1143 for (cost_classes_num = 0; | |
| 1144 cost_classes_num < ira_important_classes_num; | |
| 1145 cost_classes_num++) | |
| 1146 { | |
| 1147 cost_classes[cost_classes_num] | |
| 1148 = ira_important_classes[cost_classes_num]; | |
| 1149 cost_class_nums[cost_classes[cost_classes_num]] | |
| 1150 = cost_classes_num; | |
| 1151 } | |
| 1152 struct_costs_size | |
| 1153 = sizeof (struct costs) + sizeof (int) * (cost_classes_num - 1); | |
| 1154 /* Zero out our accumulation of the cost of each class for each | |
| 1155 allocno. */ | |
| 1156 memset (allocno_costs, 0, ira_allocnos_num * struct_costs_size); | |
| 1157 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1158 memset (in_inc_dec, 0, ira_allocnos_num * sizeof (bool)); | |
| 1159 #endif | |
| 1160 | |
| 1161 /* Scan the instructions and record each time it would save code | |
| 1162 to put a certain allocno in a certain class. */ | |
| 1163 ira_traverse_loop_tree (true, ira_loop_tree_root, | |
| 1164 process_bb_node_for_costs, NULL); | |
| 1165 | |
| 1166 memcpy (total_costs, allocno_costs, | |
| 1167 max_struct_costs_size * ira_allocnos_num); | |
| 1168 if (pass == 0) | |
| 1169 allocno_pref = allocno_pref_buffer; | |
| 1170 | |
| 1171 /* Now for each allocno look at how desirable each class is and | |
| 1172 find which class is preferred. */ | |
| 1173 for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
| 1174 { | |
| 1175 ira_allocno_t a, parent_a; | |
| 1176 int rclass, a_num, parent_a_num; | |
| 1177 ira_loop_tree_node_t parent; | |
| 1178 int best_cost, allocno_cost; | |
| 1179 enum reg_class best, alt_class; | |
| 1180 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1181 int inc_dec_p = false; | |
| 1182 #endif | |
| 1183 | |
| 1184 if (ira_regno_allocno_map[i] == NULL) | |
| 1185 continue; | |
| 1186 memset (temp_costs, 0, struct_costs_size); | |
| 1187 /* Find cost of all allocnos with the same regno. */ | |
| 1188 for (a = ira_regno_allocno_map[i]; | |
| 1189 a != NULL; | |
| 1190 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
| 1191 { | |
| 1192 a_num = ALLOCNO_NUM (a); | |
| 1193 if ((flag_ira_region == IRA_REGION_ALL | |
| 1194 || flag_ira_region == IRA_REGION_MIXED) | |
| 1195 && (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL | |
| 1196 && (parent_a = parent->regno_allocno_map[i]) != NULL | |
| 1197 /* There are no caps yet. */ | |
| 1198 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE (a)->border_allocnos, | |
| 1199 ALLOCNO_NUM (a))) | |
| 1200 { | |
| 1201 /* Propagate costs to upper levels in the region | |
| 1202 tree. */ | |
| 1203 parent_a_num = ALLOCNO_NUM (parent_a); | |
| 1204 for (k = 0; k < cost_classes_num; k++) | |
| 1205 COSTS_OF_ALLOCNO (total_costs, parent_a_num)->cost[k] | |
| 1206 += COSTS_OF_ALLOCNO (total_costs, a_num)->cost[k]; | |
| 1207 COSTS_OF_ALLOCNO (total_costs, parent_a_num)->mem_cost | |
| 1208 += COSTS_OF_ALLOCNO (total_costs, a_num)->mem_cost; | |
| 1209 } | |
| 1210 for (k = 0; k < cost_classes_num; k++) | |
| 1211 temp_costs->cost[k] | |
| 1212 += COSTS_OF_ALLOCNO (allocno_costs, a_num)->cost[k]; | |
| 1213 temp_costs->mem_cost | |
| 1214 += COSTS_OF_ALLOCNO (allocno_costs, a_num)->mem_cost; | |
| 1215 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1216 if (in_inc_dec[a_num]) | |
| 1217 inc_dec_p = true; | |
| 1218 #endif | |
| 1219 } | |
| 1220 best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; | |
| 1221 best = ALL_REGS; | |
| 1222 alt_class = NO_REGS; | |
| 1223 /* Find best common class for all allocnos with the same | |
| 1224 regno. */ | |
| 1225 for (k = 0; k < cost_classes_num; k++) | |
| 1226 { | |
| 1227 rclass = cost_classes[k]; | |
| 1228 /* Ignore classes that are too small for this operand or | |
| 1229 invalid for an operand that was auto-incremented. */ | |
| 1230 if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)] | |
| 1231 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1232 || (inc_dec_p && forbidden_inc_dec_class[rclass]) | |
| 1233 #endif | |
| 1234 #ifdef CANNOT_CHANGE_MODE_CLASS | |
| 1235 || invalid_mode_change_p (i, (enum reg_class) rclass, | |
| 1236 PSEUDO_REGNO_MODE (i)) | |
| 1237 #endif | |
| 1238 ) | |
| 1239 continue; | |
| 1240 if (temp_costs->cost[k] < best_cost) | |
| 1241 { | |
| 1242 best_cost = temp_costs->cost[k]; | |
| 1243 best = (enum reg_class) rclass; | |
| 1244 } | |
| 1245 else if (temp_costs->cost[k] == best_cost) | |
| 1246 best = ira_reg_class_union[best][rclass]; | |
| 1247 if (pass == flag_expensive_optimizations | |
| 1248 && temp_costs->cost[k] < temp_costs->mem_cost | |
| 1249 && (reg_class_size[reg_class_subunion[alt_class][rclass]] | |
| 1250 > reg_class_size[alt_class])) | |
| 1251 alt_class = reg_class_subunion[alt_class][rclass]; | |
| 1252 } | |
| 1253 alt_class = ira_class_translate[alt_class]; | |
| 1254 if (pass == flag_expensive_optimizations) | |
| 1255 { | |
| 1256 if (best_cost > temp_costs->mem_cost) | |
| 1257 best = alt_class = NO_REGS; | |
| 1258 else if (best == alt_class) | |
| 1259 alt_class = NO_REGS; | |
| 1260 setup_reg_classes (i, best, alt_class); | |
| 1261 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
| 1262 fprintf (ira_dump_file, | |
| 1263 " r%d: preferred %s, alternative %s\n", | |
| 1264 i, reg_class_names[best], reg_class_names[alt_class]); | |
| 1265 } | |
| 1266 if (best_cost > temp_costs->mem_cost) | |
| 1267 common_classes[i] = NO_REGS; | |
| 1268 else if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY) | |
| 1269 /* Make the common class the biggest class of best and | |
| 1270 alt_class. */ | |
| 1271 common_classes[i] = alt_class == NO_REGS ? best : alt_class; | |
| 1272 else | |
| 1273 /* Make the common class a cover class. Remember all | |
| 1274 allocnos with the same regno should have the same cover | |
| 1275 class. */ | |
| 1276 common_classes[i] = ira_class_translate[best]; | |
| 1277 for (a = ira_regno_allocno_map[i]; | |
| 1278 a != NULL; | |
| 1279 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
| 1280 { | |
| 1281 a_num = ALLOCNO_NUM (a); | |
| 1282 if (common_classes[i] == NO_REGS) | |
| 1283 best = NO_REGS; | |
| 1284 else | |
| 1285 { | |
| 1286 /* Finding best class which is subset of the common | |
| 1287 class. */ | |
| 1288 best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; | |
| 1289 allocno_cost = best_cost; | |
| 1290 best = ALL_REGS; | |
| 1291 for (k = 0; k < cost_classes_num; k++) | |
| 1292 { | |
| 1293 rclass = cost_classes[k]; | |
| 1294 if (! ira_class_subset_p[rclass][common_classes[i]]) | |
| 1295 continue; | |
| 1296 /* Ignore classes that are too small for this | |
| 1297 operand or invalid for an operand that was | |
| 1298 auto-incremented. */ | |
| 1299 if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)] | |
| 1300 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1301 || (inc_dec_p && forbidden_inc_dec_class[rclass]) | |
| 1302 #endif | |
| 1303 #ifdef CANNOT_CHANGE_MODE_CLASS | |
| 1304 || invalid_mode_change_p (i, (enum reg_class) rclass, | |
| 1305 PSEUDO_REGNO_MODE (i)) | |
| 1306 #endif | |
| 1307 ) | |
| 1308 ; | |
| 1309 else if (COSTS_OF_ALLOCNO (total_costs, a_num)->cost[k] | |
| 1310 < best_cost) | |
| 1311 { | |
| 1312 best_cost | |
| 1313 = COSTS_OF_ALLOCNO (total_costs, a_num)->cost[k]; | |
| 1314 allocno_cost | |
| 1315 = COSTS_OF_ALLOCNO (allocno_costs, a_num)->cost[k]; | |
| 1316 best = (enum reg_class) rclass; | |
| 1317 } | |
| 1318 else if (COSTS_OF_ALLOCNO (total_costs, a_num)->cost[k] | |
| 1319 == best_cost) | |
| 1320 { | |
| 1321 best = ira_reg_class_union[best][rclass]; | |
| 1322 allocno_cost | |
| 1323 = MAX (allocno_cost, | |
| 1324 COSTS_OF_ALLOCNO (allocno_costs, | |
| 1325 a_num)->cost[k]); | |
| 1326 } | |
| 1327 } | |
| 1328 ALLOCNO_COVER_CLASS_COST (a) = allocno_cost; | |
| 1329 } | |
| 1330 ira_assert (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY | |
| 1331 || ira_class_translate[best] == common_classes[i]); | |
| 1332 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL | |
| 1333 && (pass == 0 || allocno_pref[a_num] != best)) | |
| 1334 { | |
| 1335 fprintf (ira_dump_file, " a%d (r%d,", a_num, i); | |
| 1336 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
| 1337 fprintf (ira_dump_file, "b%d", bb->index); | |
| 1338 else | |
| 1339 fprintf (ira_dump_file, "l%d", | |
| 1340 ALLOCNO_LOOP_TREE_NODE (a)->loop->num); | |
| 1341 fprintf (ira_dump_file, ") best %s, cover %s\n", | |
| 1342 reg_class_names[best], | |
| 1343 reg_class_names[common_classes[i]]); | |
| 1344 } | |
| 1345 allocno_pref[a_num] = best; | |
| 1346 } | |
| 1347 } | |
| 1348 | |
| 1349 if (internal_flag_ira_verbose > 4 && ira_dump_file) | |
| 1350 { | |
| 1351 print_costs (ira_dump_file); | |
| 1352 fprintf (ira_dump_file,"\n"); | |
| 1353 } | |
| 1354 } | |
| 1355 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1356 ira_free (in_inc_dec); | |
| 1357 #endif | |
| 1358 } | |
| 1359 | |
| 1360 | |
| 1361 | |
| 1362 /* Process moves involving hard regs to modify allocno hard register | |
| 1363 costs. We can do this only after determining allocno cover class. | |
| 1364 If a hard register forms a register class, than moves with the hard | |
| 1365 register are already taken into account in class costs for the | |
| 1366 allocno. */ | |
| 1367 static void | |
| 1368 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node) | |
| 1369 { | |
| 1370 int i, freq, cost, src_regno, dst_regno, hard_regno; | |
| 1371 bool to_p; | |
| 1372 ira_allocno_t a; | |
| 1373 enum reg_class rclass, hard_reg_class; | |
| 1374 enum machine_mode mode; | |
| 1375 basic_block bb; | |
| 1376 rtx insn, set, src, dst; | |
| 1377 | |
| 1378 bb = loop_tree_node->bb; | |
| 1379 if (bb == NULL) | |
| 1380 return; | |
| 1381 freq = REG_FREQ_FROM_BB (bb); | |
| 1382 if (freq == 0) | |
| 1383 freq = 1; | |
| 1384 FOR_BB_INSNS (bb, insn) | |
| 1385 { | |
| 1386 if (! INSN_P (insn)) | |
| 1387 continue; | |
| 1388 set = single_set (insn); | |
| 1389 if (set == NULL_RTX) | |
| 1390 continue; | |
| 1391 dst = SET_DEST (set); | |
| 1392 src = SET_SRC (set); | |
| 1393 if (! REG_P (dst) || ! REG_P (src)) | |
| 1394 continue; | |
| 1395 dst_regno = REGNO (dst); | |
| 1396 src_regno = REGNO (src); | |
| 1397 if (dst_regno >= FIRST_PSEUDO_REGISTER | |
| 1398 && src_regno < FIRST_PSEUDO_REGISTER) | |
| 1399 { | |
| 1400 hard_regno = src_regno; | |
| 1401 to_p = true; | |
| 1402 a = ira_curr_regno_allocno_map[dst_regno]; | |
| 1403 } | |
| 1404 else if (src_regno >= FIRST_PSEUDO_REGISTER | |
| 1405 && dst_regno < FIRST_PSEUDO_REGISTER) | |
| 1406 { | |
| 1407 hard_regno = dst_regno; | |
| 1408 to_p = false; | |
| 1409 a = ira_curr_regno_allocno_map[src_regno]; | |
| 1410 } | |
| 1411 else | |
| 1412 continue; | |
| 1413 rclass = ALLOCNO_COVER_CLASS (a); | |
| 1414 if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], hard_regno)) | |
| 1415 continue; | |
| 1416 i = ira_class_hard_reg_index[rclass][hard_regno]; | |
| 1417 if (i < 0) | |
| 1418 continue; | |
| 1419 mode = ALLOCNO_MODE (a); | |
| 1420 hard_reg_class = REGNO_REG_CLASS (hard_regno); | |
|
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1421 cost |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1422 = (to_p ? ira_get_register_move_cost (mode, hard_reg_class, rclass) |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1423 : ira_get_register_move_cost (mode, rclass, hard_reg_class)) * freq; |
| 0 | 1424 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a), rclass, |
| 1425 ALLOCNO_COVER_CLASS_COST (a)); | |
| 1426 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a), | |
| 1427 rclass, 0); | |
| 1428 ALLOCNO_HARD_REG_COSTS (a)[i] -= cost; | |
| 1429 ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost; | |
| 1430 ALLOCNO_COVER_CLASS_COST (a) = MIN (ALLOCNO_COVER_CLASS_COST (a), | |
| 1431 ALLOCNO_HARD_REG_COSTS (a)[i]); | |
| 1432 } | |
| 1433 } | |
| 1434 | |
| 1435 /* After we find hard register and memory costs for allocnos, define | |
| 1436 its cover class and modify hard register cost because insns moving | |
| 1437 allocno to/from hard registers. */ | |
| 1438 static void | |
| 1439 setup_allocno_cover_class_and_costs (void) | |
| 1440 { | |
| 1441 int i, j, n, regno, num; | |
| 1442 int *reg_costs; | |
| 1443 enum reg_class cover_class, rclass; | |
| 1444 enum machine_mode mode; | |
| 1445 HARD_REG_SET *pref; | |
| 1446 ira_allocno_t a; | |
| 1447 ira_allocno_iterator ai; | |
| 1448 | |
| 1449 FOR_EACH_ALLOCNO (a, ai) | |
| 1450 { | |
| 1451 i = ALLOCNO_NUM (a); | |
| 1452 mode = ALLOCNO_MODE (a); | |
| 1453 cover_class = common_classes[ALLOCNO_REGNO (a)]; | |
| 1454 ira_assert (allocno_pref[i] == NO_REGS || cover_class != NO_REGS); | |
| 1455 ALLOCNO_MEMORY_COST (a) = COSTS_OF_ALLOCNO (allocno_costs, i)->mem_cost; | |
| 1456 ira_set_allocno_cover_class (a, cover_class); | |
| 1457 if (cover_class == NO_REGS) | |
| 1458 continue; | |
| 1459 ALLOCNO_AVAILABLE_REGS_NUM (a) = ira_available_class_regs[cover_class]; | |
| 1460 pref = ®_class_contents[allocno_pref[i]]; | |
| 1461 if (optimize && ALLOCNO_COVER_CLASS (a) != allocno_pref[i]) | |
| 1462 { | |
| 1463 n = ira_class_hard_regs_num[cover_class]; | |
| 1464 ALLOCNO_HARD_REG_COSTS (a) | |
| 1465 = reg_costs = ira_allocate_cost_vector (cover_class); | |
| 1466 for (j = n - 1; j >= 0; j--) | |
| 1467 { | |
| 1468 regno = ira_class_hard_regs[cover_class][j]; | |
| 1469 if (TEST_HARD_REG_BIT (*pref, regno)) | |
| 1470 reg_costs[j] = ALLOCNO_COVER_CLASS_COST (a); | |
| 1471 else | |
| 1472 { | |
| 1473 rclass = REGNO_REG_CLASS (regno); | |
| 1474 num = cost_class_nums[rclass]; | |
| 1475 if (num < 0) | |
| 1476 { | |
| 1477 /* The hard register class is not a cover class or a | |
| 1478 class not fully inside in a cover class -- use | |
| 1479 the allocno cover class. */ | |
| 1480 ira_assert (ira_hard_regno_cover_class[regno] | |
| 1481 == cover_class); | |
| 1482 num = cost_class_nums[cover_class]; | |
| 1483 } | |
| 1484 reg_costs[j] = COSTS_OF_ALLOCNO (allocno_costs, i)->cost[num]; | |
| 1485 } | |
| 1486 } | |
| 1487 } | |
| 1488 } | |
| 1489 if (optimize) | |
| 1490 ira_traverse_loop_tree (true, ira_loop_tree_root, | |
| 1491 process_bb_node_for_hard_reg_moves, NULL); | |
| 1492 } | |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 /* Function called once during compiler work. */ | |
| 1497 void | |
| 1498 ira_init_costs_once (void) | |
| 1499 { | |
| 1500 int i; | |
| 1501 | |
| 1502 init_cost = NULL; | |
| 1503 for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
| 1504 { | |
| 1505 op_costs[i] = NULL; | |
| 1506 this_op_costs[i] = NULL; | |
| 1507 } | |
| 1508 temp_costs = NULL; | |
| 1509 cost_classes = NULL; | |
| 1510 } | |
| 1511 | |
| 1512 /* Free allocated temporary cost vectors. */ | |
| 1513 static void | |
| 1514 free_ira_costs (void) | |
| 1515 { | |
| 1516 int i; | |
| 1517 | |
| 1518 if (init_cost != NULL) | |
| 1519 free (init_cost); | |
| 1520 init_cost = NULL; | |
| 1521 for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
| 1522 { | |
| 1523 if (op_costs[i] != NULL) | |
| 1524 free (op_costs[i]); | |
| 1525 if (this_op_costs[i] != NULL) | |
| 1526 free (this_op_costs[i]); | |
| 1527 op_costs[i] = this_op_costs[i] = NULL; | |
| 1528 } | |
| 1529 if (temp_costs != NULL) | |
| 1530 free (temp_costs); | |
| 1531 temp_costs = NULL; | |
| 1532 if (cost_classes != NULL) | |
| 1533 free (cost_classes); | |
| 1534 cost_classes = NULL; | |
| 1535 } | |
| 1536 | |
| 1537 /* This is called each time register related information is | |
| 1538 changed. */ | |
| 1539 void | |
| 1540 ira_init_costs (void) | |
| 1541 { | |
| 1542 int i; | |
| 1543 | |
| 1544 free_ira_costs (); | |
| 1545 max_struct_costs_size | |
| 1546 = sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1); | |
| 1547 /* Don't use ira_allocate because vectors live through several IRA calls. */ | |
| 1548 init_cost = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1549 init_cost->mem_cost = 1000000; | |
| 1550 for (i = 0; i < ira_important_classes_num; i++) | |
| 1551 init_cost->cost[i] = 1000000; | |
| 1552 for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
| 1553 { | |
| 1554 op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1555 this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1556 } | |
| 1557 temp_costs = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1558 cost_classes = (enum reg_class *) xmalloc (sizeof (enum reg_class) | |
| 1559 * ira_important_classes_num); | |
| 1560 } | |
| 1561 | |
| 1562 /* Function called once at the end of compiler work. */ | |
| 1563 void | |
| 1564 ira_finish_costs_once (void) | |
| 1565 { | |
| 1566 free_ira_costs (); | |
| 1567 } | |
| 1568 | |
| 1569 | |
| 1570 | |
| 1571 /* Entry function which defines cover class, memory and hard register | |
| 1572 costs for each allocno. */ | |
| 1573 void | |
| 1574 ira_costs (void) | |
| 1575 { | |
| 1576 allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size | |
| 1577 * ira_allocnos_num); | |
| 1578 total_costs = (struct costs *) ira_allocate (max_struct_costs_size | |
| 1579 * ira_allocnos_num); | |
| 1580 allocno_pref_buffer | |
| 1581 = (enum reg_class *) ira_allocate (sizeof (enum reg_class) | |
| 1582 * ira_allocnos_num); | |
| 1583 common_classes | |
| 1584 = (enum reg_class *) ira_allocate (sizeof (enum reg_class) | |
| 1585 * max_reg_num ()); | |
| 1586 find_allocno_class_costs (); | |
| 1587 setup_allocno_cover_class_and_costs (); | |
| 1588 ira_free (common_classes); | |
| 1589 ira_free (allocno_pref_buffer); | |
| 1590 ira_free (total_costs); | |
| 1591 ira_free (allocno_costs); | |
| 1592 } | |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 /* Change hard register costs for allocnos which lives through | |
| 1597 function calls. This is called only when we found all intersected | |
| 1598 calls during building allocno live ranges. */ | |
| 1599 void | |
| 1600 ira_tune_allocno_costs_and_cover_classes (void) | |
| 1601 { | |
| 1602 int j, n, regno; | |
| 1603 int cost, min_cost, *reg_costs; | |
| 1604 enum reg_class cover_class, rclass; | |
| 1605 enum machine_mode mode; | |
| 1606 ira_allocno_t a; | |
| 1607 ira_allocno_iterator ai; | |
| 1608 | |
| 1609 FOR_EACH_ALLOCNO (a, ai) | |
| 1610 { | |
| 1611 cover_class = ALLOCNO_COVER_CLASS (a); | |
| 1612 if (cover_class == NO_REGS) | |
| 1613 continue; | |
| 1614 mode = ALLOCNO_MODE (a); | |
| 1615 n = ira_class_hard_regs_num[cover_class]; | |
| 1616 min_cost = INT_MAX; | |
| 1617 if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0) | |
| 1618 { | |
| 1619 ira_allocate_and_set_costs | |
| 1620 (&ALLOCNO_HARD_REG_COSTS (a), cover_class, | |
| 1621 ALLOCNO_COVER_CLASS_COST (a)); | |
| 1622 reg_costs = ALLOCNO_HARD_REG_COSTS (a); | |
| 1623 for (j = n - 1; j >= 0; j--) | |
| 1624 { | |
| 1625 regno = ira_class_hard_regs[cover_class][j]; | |
| 1626 rclass = REGNO_REG_CLASS (regno); | |
| 1627 cost = 0; | |
| 1628 if (! ira_hard_reg_not_in_set_p (regno, mode, call_used_reg_set) | |
| 1629 || HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) | |
| 1630 cost += (ALLOCNO_CALL_FREQ (a) | |
| 1631 * (ira_memory_move_cost[mode][rclass][0] | |
| 1632 + ira_memory_move_cost[mode][rclass][1])); | |
| 1633 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER | |
| 1634 cost += ((ira_memory_move_cost[mode][rclass][0] | |
| 1635 + ira_memory_move_cost[mode][rclass][1]) | |
| 1636 * ALLOCNO_FREQ (a) | |
| 1637 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2); | |
| 1638 #endif | |
| 1639 reg_costs[j] += cost; | |
| 1640 if (min_cost > reg_costs[j]) | |
| 1641 min_cost = reg_costs[j]; | |
| 1642 } | |
| 1643 } | |
| 1644 if (min_cost != INT_MAX) | |
| 1645 ALLOCNO_COVER_CLASS_COST (a) = min_cost; | |
| 1646 } | |
| 1647 } |