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1 ;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620,
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2 ;; and PowerPC 630 processors.
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3 ;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
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4 ;;
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2")
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22 (define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx")
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23 (define_cpu_unit "fpu_6xx" "ppc6xxfp")
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24 (define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2")
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25 (define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx")
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26
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27 ;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
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28 ;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
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29 ;; MCIU used for imul/idiv and moves from/to spr
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30 ;; LSU 2 stage pipelined
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31 ;; FPU 3 stage pipelined
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32 ;; Max issue 4 insns/clock cycle
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33
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34 ;; PPC604e is PPC604 with larger caches and a CRU. In the 604
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35 ;; the CR logical operations are handled in the BPU.
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36 ;; In the 604e, the CRU shares bus with BPU so only one condition
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37 ;; register or branch insn can be issued per clock. Not modelled.
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38
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39 ;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
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40 ;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
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41 ;; Max issue 4 insns/clock cycle
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42 ;; Out-of-order execution, in-order completion
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43
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44 ;; No following instruction can dispatch in the same cycle as a branch
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45 ;; instruction. Not modelled. This is no problem if RCSP is not
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46 ;; enabled since the scheduler stops a schedule when it gets to a branch.
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47
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48 ;; Four insns can be dispatched per cycle.
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49
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50 (define_insn_reservation "ppc604-load" 2
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51 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
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52 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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53 "lsu_6xx")
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54
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55 (define_insn_reservation "ppc604-fpload" 3
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56 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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57 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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58 "lsu_6xx")
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59
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60 (define_insn_reservation "ppc604-store" 3
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61 (and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
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62 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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63 "lsu_6xx")
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64
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65 (define_insn_reservation "ppc604-llsc" 3
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66 (and (eq_attr "type" "load_l,store_c")
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67 (eq_attr "cpu" "ppc604,ppc604e"))
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68 "lsu_6xx")
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69
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70 (define_insn_reservation "ppc630-llsc" 4
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71 (and (eq_attr "type" "load_l,store_c")
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72 (eq_attr "cpu" "ppc620,ppc630"))
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73 "lsu_6xx")
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74
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75 (define_insn_reservation "ppc604-integer" 1
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76 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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77 var_shift_rotate,cntlz,exts")
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78 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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79 "iu1_6xx|iu2_6xx")
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80
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81 (define_insn_reservation "ppc604-two" 1
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82 (and (eq_attr "type" "two")
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83 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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84 "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
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85
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86 (define_insn_reservation "ppc604-three" 1
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87 (and (eq_attr "type" "three")
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88 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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89 "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
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90
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91 (define_insn_reservation "ppc604-imul" 4
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92 (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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93 (eq_attr "cpu" "ppc604"))
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94 "mciu_6xx*2")
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95
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96 (define_insn_reservation "ppc604e-imul" 2
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97 (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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98 (eq_attr "cpu" "ppc604e"))
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99 "mciu_6xx")
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100
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101 (define_insn_reservation "ppc620-imul" 5
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102 (and (eq_attr "type" "imul,imul_compare")
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103 (eq_attr "cpu" "ppc620,ppc630"))
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104 "mciu_6xx*3")
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105
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106 (define_insn_reservation "ppc620-imul2" 4
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107 (and (eq_attr "type" "imul2")
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108 (eq_attr "cpu" "ppc620,ppc630"))
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109 "mciu_6xx*3")
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110
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111 (define_insn_reservation "ppc620-imul3" 3
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112 (and (eq_attr "type" "imul3")
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113 (eq_attr "cpu" "ppc620,ppc630"))
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114 "mciu_6xx*3")
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115
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116 (define_insn_reservation "ppc620-lmul" 7
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117 (and (eq_attr "type" "lmul,lmul_compare")
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118 (eq_attr "cpu" "ppc620,ppc630"))
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119 "mciu_6xx*5")
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120
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121 (define_insn_reservation "ppc604-idiv" 20
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122 (and (eq_attr "type" "idiv")
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123 (eq_attr "cpu" "ppc604,ppc604e"))
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124 "mciu_6xx*19")
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125
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126 (define_insn_reservation "ppc620-idiv" 37
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127 (and (eq_attr "type" "idiv")
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128 (eq_attr "cpu" "ppc620"))
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129 "mciu_6xx*36")
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130
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131 (define_insn_reservation "ppc630-idiv" 21
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132 (and (eq_attr "type" "idiv")
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133 (eq_attr "cpu" "ppc630"))
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134 "mciu_6xx*20")
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135
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136 (define_insn_reservation "ppc620-ldiv" 37
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137 (and (eq_attr "type" "ldiv")
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138 (eq_attr "cpu" "ppc620,ppc630"))
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139 "mciu_6xx*36")
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140
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141 (define_insn_reservation "ppc604-compare" 3
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142 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
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143 var_delayed_compare")
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144 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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145 "(iu1_6xx|iu2_6xx)")
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146
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147 ; FPU PPC604{,e},PPC620
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148 (define_insn_reservation "ppc604-fpcompare" 5
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149 (and (eq_attr "type" "fpcompare")
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150 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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151 "fpu_6xx")
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152
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153 (define_insn_reservation "ppc604-fp" 3
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154 (and (eq_attr "type" "fp")
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155 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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156 "fpu_6xx")
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157
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158 (define_insn_reservation "ppc604-dmul" 3
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159 (and (eq_attr "type" "dmul")
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160 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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161 "fpu_6xx")
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162
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163 ; Divides are not pipelined
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164 (define_insn_reservation "ppc604-sdiv" 18
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165 (and (eq_attr "type" "sdiv")
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166 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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167 "fpu_6xx*18")
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168
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169 (define_insn_reservation "ppc604-ddiv" 32
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170 (and (eq_attr "type" "ddiv")
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171 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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172 "fpu_6xx*32")
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173
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174 (define_insn_reservation "ppc620-ssqrt" 31
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175 (and (eq_attr "type" "ssqrt")
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176 (eq_attr "cpu" "ppc620"))
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177 "fpu_6xx*31")
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178
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179 (define_insn_reservation "ppc620-dsqrt" 31
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180 (and (eq_attr "type" "dsqrt")
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181 (eq_attr "cpu" "ppc620"))
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182 "fpu_6xx*31")
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183
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184
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185 ; 2xFPU PPC630
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186 (define_insn_reservation "ppc630-fpcompare" 5
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187 (and (eq_attr "type" "fpcompare")
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188 (eq_attr "cpu" "ppc630"))
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189 "fpu1_6xx|fpu2_6xx")
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190
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191 (define_insn_reservation "ppc630-fp" 3
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192 (and (eq_attr "type" "fp,dmul")
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193 (eq_attr "cpu" "ppc630"))
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194 "fpu1_6xx|fpu2_6xx")
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195
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196 (define_insn_reservation "ppc630-sdiv" 17
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197 (and (eq_attr "type" "sdiv")
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198 (eq_attr "cpu" "ppc630"))
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199 "fpu1_6xx*17|fpu2_6xx*17")
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200
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201 (define_insn_reservation "ppc630-ddiv" 21
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202 (and (eq_attr "type" "ddiv")
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203 (eq_attr "cpu" "ppc630"))
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204 "fpu1_6xx*21|fpu2_6xx*21")
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205
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206 (define_insn_reservation "ppc630-ssqrt" 18
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207 (and (eq_attr "type" "ssqrt")
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208 (eq_attr "cpu" "ppc630"))
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209 "fpu1_6xx*18|fpu2_6xx*18")
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210
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211 (define_insn_reservation "ppc630-dsqrt" 25
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212 (and (eq_attr "type" "dsqrt")
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213 (eq_attr "cpu" "ppc630"))
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214 "fpu1_6xx*25|fpu2_6xx*25")
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215
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216 (define_insn_reservation "ppc604-mfcr" 3
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217 (and (eq_attr "type" "mfcr")
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218 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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219 "mciu_6xx")
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220
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221 (define_insn_reservation "ppc604-mtcr" 2
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222 (and (eq_attr "type" "mtcr")
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223 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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224 "iu1_6xx|iu2_6xx")
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225
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226 (define_insn_reservation "ppc604-crlogical" 2
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227 (and (eq_attr "type" "cr_logical,delayed_cr")
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228 (eq_attr "cpu" "ppc604"))
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229 "bpu_6xx")
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230
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231 (define_insn_reservation "ppc604e-crlogical" 2
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232 (and (eq_attr "type" "cr_logical,delayed_cr")
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233 (eq_attr "cpu" "ppc604e,ppc620,ppc630"))
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234 "cru_6xx")
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235
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236 (define_insn_reservation "ppc604-mtjmpr" 2
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237 (and (eq_attr "type" "mtjmpr")
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238 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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239 "mciu_6xx")
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240
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241 (define_insn_reservation "ppc604-mfjmpr" 3
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242 (and (eq_attr "type" "mfjmpr")
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243 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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244 "mciu_6xx")
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245
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246 (define_insn_reservation "ppc630-mfjmpr" 2
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247 (and (eq_attr "type" "mfjmpr")
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248 (eq_attr "cpu" "ppc630"))
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249 "mciu_6xx")
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250
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251 (define_insn_reservation "ppc604-jmpreg" 1
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252 (and (eq_attr "type" "jmpreg,branch")
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253 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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254 "bpu_6xx")
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255
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256 (define_insn_reservation "ppc604-isync" 0
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257 (and (eq_attr "type" "isync")
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258 (eq_attr "cpu" "ppc604,ppc604e"))
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259 "bpu_6xx")
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260
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261 (define_insn_reservation "ppc630-isync" 6
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262 (and (eq_attr "type" "isync")
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263 (eq_attr "cpu" "ppc620,ppc630"))
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264 "bpu_6xx")
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265
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266 (define_insn_reservation "ppc604-sync" 35
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267 (and (eq_attr "type" "sync")
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268 (eq_attr "cpu" "ppc604,ppc604e"))
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269 "lsu_6xx")
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270
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271 (define_insn_reservation "ppc630-sync" 26
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272 (and (eq_attr "type" "sync")
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273 (eq_attr "cpu" "ppc620,ppc630"))
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274 "lsu_6xx")
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275
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