Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/arm/arm-generic.md @ 158:494b0b89df80 default tip
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| author | Shinji KONO <kono@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 25 May 2020 18:13:55 +0900 |
| parents | 1830386684a0 |
| children |
| rev | line source |
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| 0 | 1 ;; Generic ARM Pipeline Description |
| 145 | 2 ;; Copyright (C) 2003-2020 Free Software Foundation, Inc. |
| 0 | 3 ;; |
| 4 ;; This file is part of GCC. | |
| 5 ;; | |
| 6 ;; GCC is free software; you can redistribute it and/or modify it | |
| 7 ;; under the terms of the GNU General Public License as published by | |
| 8 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 9 ;; any later version. | |
| 10 ;; | |
| 11 ;; GCC is distributed in the hope that it will be useful, but | |
| 12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 ;; General Public License for more details. | |
| 15 ;; | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. */ | |
| 19 | |
| 20 (define_automaton "arm") | |
| 21 | |
| 22 ;; Write buffer | |
| 23 ; | |
| 24 ; Strictly, we should model a 4-deep write buffer for ARM7xx based chips | |
| 25 ; | |
| 26 ; The write buffer on some of the arm6 processors is hard to model exactly. | |
| 27 ; There is room in the buffer for up to two addresses and up to eight words | |
| 28 ; of memory, but the two needn't be split evenly. When writing the two | |
| 29 ; addresses are fully pipelined. However, a read from memory that is not | |
| 30 ; currently in the cache will block until the writes have completed. | |
| 31 ; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so | |
| 32 ; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous | |
| 33 ; (they aren't allowed to be at present) then there is a startup cost of 1MCLK | |
| 34 ; cycle to add as well. | |
| 35 (define_cpu_unit "write_buf" "arm") | |
| 36 | |
| 37 ;; Write blockage unit | |
| 38 ; | |
| 39 ; The write_blockage unit models (partially), the fact that reads will stall | |
| 40 ; until the write buffer empties. | |
| 41 (define_cpu_unit "write_blockage" "arm") | |
| 42 | |
| 43 ;; Core | |
| 44 ; | |
| 45 (define_cpu_unit "core" "arm") | |
| 46 | |
| 47 (define_insn_reservation "store_wbuf" 5 | |
| 48 (and (eq_attr "generic_sched" "yes") | |
| 49 (and (eq_attr "model_wbuf" "yes") | |
| 111 | 50 (eq_attr "type" "store_4"))) |
| 0 | 51 "core+write_buf*3+write_blockage*5") |
| 52 | |
| 53 (define_insn_reservation "store2_wbuf" 7 | |
| 54 (and (eq_attr "generic_sched" "yes") | |
| 55 (and (eq_attr "model_wbuf" "yes") | |
| 111 | 56 (eq_attr "type" "store_8"))) |
| 0 | 57 "core+write_buf*4+write_blockage*7") |
| 58 | |
| 59 (define_insn_reservation "store3_wbuf" 9 | |
| 60 (and (eq_attr "generic_sched" "yes") | |
| 61 (and (eq_attr "model_wbuf" "yes") | |
| 111 | 62 (eq_attr "type" "store_12"))) |
| 0 | 63 "core+write_buf*5+write_blockage*9") |
| 64 | |
| 65 (define_insn_reservation "store4_wbuf" 11 | |
| 66 (and (eq_attr "generic_sched" "yes") | |
| 67 (and (eq_attr "model_wbuf" "yes") | |
| 111 | 68 (eq_attr "type" "store_16"))) |
| 0 | 69 "core+write_buf*6+write_blockage*11") |
| 70 | |
| 71 (define_insn_reservation "store2" 3 | |
| 72 (and (eq_attr "generic_sched" "yes") | |
| 73 (and (eq_attr "model_wbuf" "no") | |
| 111 | 74 (eq_attr "type" "store_8"))) |
| 0 | 75 "core*3") |
| 76 | |
| 77 (define_insn_reservation "store3" 4 | |
| 78 (and (eq_attr "generic_sched" "yes") | |
| 79 (and (eq_attr "model_wbuf" "no") | |
| 111 | 80 (eq_attr "type" "store_12"))) |
| 0 | 81 "core*4") |
| 82 | |
| 83 (define_insn_reservation "store4" 5 | |
| 84 (and (eq_attr "generic_sched" "yes") | |
| 85 (and (eq_attr "model_wbuf" "no") | |
| 111 | 86 (eq_attr "type" "store_16"))) |
| 0 | 87 "core*5") |
| 88 | |
| 89 (define_insn_reservation "store_ldsched" 1 | |
| 90 (and (eq_attr "generic_sched" "yes") | |
| 91 (and (eq_attr "ldsched" "yes") | |
| 111 | 92 (eq_attr "type" "store_4"))) |
| 0 | 93 "core") |
| 94 | |
| 95 (define_insn_reservation "load_ldsched_xscale" 3 | |
| 96 (and (eq_attr "generic_sched" "yes") | |
| 97 (and (eq_attr "ldsched" "yes") | |
| 111 | 98 (and (eq_attr "type" "load_byte,load_4") |
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63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
99 (eq_attr "tune" "xscale,iwmmxt,iwmmxt2")))) |
| 0 | 100 "core") |
| 101 | |
| 102 (define_insn_reservation "load_ldsched" 2 | |
| 103 (and (eq_attr "generic_sched" "yes") | |
| 104 (and (eq_attr "ldsched" "yes") | |
| 111 | 105 (and (eq_attr "type" "load_byte,load_4") |
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63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
106 (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2")))) |
| 0 | 107 "core") |
| 108 | |
| 109 (define_insn_reservation "load_or_store" 2 | |
| 110 (and (eq_attr "generic_sched" "yes") | |
| 111 (and (eq_attr "ldsched" "!yes") | |
| 111 | 112 (eq_attr "type" "load_byte,load_4,load_8,load_12,load_16,store_4"))) |
| 0 | 113 "core*2") |
| 114 | |
| 115 (define_insn_reservation "mult" 16 | |
| 116 (and (eq_attr "generic_sched" "yes") | |
| 111 | 117 (and (eq_attr "ldsched" "no") |
| 118 (ior (eq_attr "mul32" "yes") | |
| 145 | 119 (eq_attr "widen_mul64" "yes")))) |
| 0 | 120 "core*16") |
| 121 | |
| 122 (define_insn_reservation "mult_ldsched_strongarm" 3 | |
| 123 (and (eq_attr "generic_sched" "yes") | |
| 124 (and (eq_attr "ldsched" "yes") | |
| 145 | 125 (and (eq_attr "tune" "strongarm") |
| 111 | 126 (ior (eq_attr "mul32" "yes") |
| 145 | 127 (eq_attr "widen_mul64" "yes"))))) |
| 0 | 128 "core*2") |
| 129 | |
| 130 (define_insn_reservation "mult_ldsched" 4 | |
| 131 (and (eq_attr "generic_sched" "yes") | |
| 132 (and (eq_attr "ldsched" "yes") | |
| 145 | 133 (and (eq_attr "tune" "!strongarm") |
| 111 | 134 (ior (eq_attr "mul32" "yes") |
| 145 | 135 (eq_attr "widen_mul64" "yes"))))) |
| 0 | 136 "core*4") |
| 137 | |
| 138 (define_insn_reservation "multi_cycle" 32 | |
| 139 (and (eq_attr "generic_sched" "yes") | |
| 140 (and (eq_attr "core_cycles" "multi") | |
| 111 | 141 (and (eq_attr "type" "!load_byte,load_4,load_8,load_12,load_16,\ |
| 142 store_4,store_8,store_12,store_16") | |
| 143 (not (ior (eq_attr "mul32" "yes") | |
| 145 | 144 (eq_attr "widen_mul64" "yes")))))) |
| 0 | 145 "core*32") |
| 146 | |
| 147 (define_insn_reservation "single_cycle" 1 | |
| 148 (and (eq_attr "generic_sched" "yes") | |
| 149 (eq_attr "core_cycles" "single")) | |
| 150 "core") |