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comparison gcc/config/arm/cortex-a5.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 561a7518be6b
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; ARM Cortex-A5 pipeline description 1 ;; ARM Cortex-A5 pipeline description
2 ;; Copyright (C) 2010 Free Software Foundation, Inc. 2 ;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery. 3 ;; Contributed by CodeSourcery.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
56 ;; ALU instructions. 56 ;; ALU instructions.
57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
58 58
59 (define_insn_reservation "cortex_a5_alu" 2 59 (define_insn_reservation "cortex_a5_alu" 2
60 (and (eq_attr "tune" "cortexa5") 60 (and (eq_attr "tune" "cortexa5")
61 (eq_attr "type" "alu")) 61 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
62 alu_sreg,alus_sreg,logic_reg,logics_reg,\
63 adc_imm,adcs_imm,adc_reg,adcs_reg,\
64 adr,bfm,clz,rbit,rev,alu_dsp_reg,\
65 shift_imm,shift_reg,\
66 mov_imm,mov_reg,mvn_imm,mvn_reg,\
67 mrs,multiple,no_insn"))
62 "cortex_a5_ex1") 68 "cortex_a5_ex1")
63 69
64 (define_insn_reservation "cortex_a5_alu_shift" 2 70 (define_insn_reservation "cortex_a5_alu_shift" 2
65 (and (eq_attr "tune" "cortexa5") 71 (and (eq_attr "tune" "cortexa5")
66 (eq_attr "type" "alu_shift,alu_shift_reg")) 72 (eq_attr "type" "extend,\
73 alu_shift_imm,alus_shift_imm,\
74 logic_shift_imm,logics_shift_imm,\
75 alu_shift_reg,alus_shift_reg,\
76 logic_shift_reg,logics_shift_reg,\
77 mov_shift,mov_shift_reg,\
78 mvn_shift,mvn_shift_reg"))
67 "cortex_a5_ex1") 79 "cortex_a5_ex1")
68 80
69 ;; Forwarding path for unshifted operands. 81 ;; Forwarding path for unshifted operands.
70 82
71 (define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" 83 (define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
78 ;; The multiplier pipeline can forward results from wr stage only so 90 ;; The multiplier pipeline can forward results from wr stage only so
79 ;; there's no need to specify bypasses). 91 ;; there's no need to specify bypasses).
80 92
81 (define_insn_reservation "cortex_a5_mul" 2 93 (define_insn_reservation "cortex_a5_mul" 2
82 (and (eq_attr "tune" "cortexa5") 94 (and (eq_attr "tune" "cortexa5")
83 (eq_attr "type" "mult")) 95 (ior (eq_attr "mul32" "yes")
96 (eq_attr "mul64" "yes")))
84 "cortex_a5_ex1") 97 "cortex_a5_ex1")
85 98
86 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 99 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
87 ;; Load/store instructions. 100 ;; Load/store instructions.
88 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 101 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
91 ;; the ex1 stage (the first stage we care about for scheduling purposes). The 104 ;; the ex1 stage (the first stage we care about for scheduling purposes). The
92 ;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr. 105 ;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
93 106
94 (define_insn_reservation "cortex_a5_load1" 2 107 (define_insn_reservation "cortex_a5_load1" 2
95 (and (eq_attr "tune" "cortexa5") 108 (and (eq_attr "tune" "cortexa5")
96 (eq_attr "type" "load_byte,load1")) 109 (eq_attr "type" "load_byte,load_4"))
97 "cortex_a5_ex1") 110 "cortex_a5_ex1")
98 111
99 (define_insn_reservation "cortex_a5_store1" 0 112 (define_insn_reservation "cortex_a5_store1" 0
100 (and (eq_attr "tune" "cortexa5") 113 (and (eq_attr "tune" "cortexa5")
101 (eq_attr "type" "store1")) 114 (eq_attr "type" "store_4"))
102 "cortex_a5_ex1") 115 "cortex_a5_ex1")
103 116
104 (define_insn_reservation "cortex_a5_load2" 3 117 (define_insn_reservation "cortex_a5_load2" 3
105 (and (eq_attr "tune" "cortexa5") 118 (and (eq_attr "tune" "cortexa5")
106 (eq_attr "type" "load2")) 119 (eq_attr "type" "load_8"))
107 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") 120 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
108 121
109 (define_insn_reservation "cortex_a5_store2" 0 122 (define_insn_reservation "cortex_a5_store2" 0
110 (and (eq_attr "tune" "cortexa5") 123 (and (eq_attr "tune" "cortexa5")
111 (eq_attr "type" "store2")) 124 (eq_attr "type" "store_8"))
112 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") 125 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
113 126
114 (define_insn_reservation "cortex_a5_load3" 4 127 (define_insn_reservation "cortex_a5_load3" 4
115 (and (eq_attr "tune" "cortexa5") 128 (and (eq_attr "tune" "cortexa5")
116 (eq_attr "type" "load3")) 129 (eq_attr "type" "load_12"))
117 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ 130 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
118 cortex_a5_ex1") 131 cortex_a5_ex1")
119 132
120 (define_insn_reservation "cortex_a5_store3" 0 133 (define_insn_reservation "cortex_a5_store3" 0
121 (and (eq_attr "tune" "cortexa5") 134 (and (eq_attr "tune" "cortexa5")
122 (eq_attr "type" "store3")) 135 (eq_attr "type" "store_12"))
123 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ 136 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
124 cortex_a5_ex1") 137 cortex_a5_ex1")
125 138
126 (define_insn_reservation "cortex_a5_load4" 5 139 (define_insn_reservation "cortex_a5_load4" 5
127 (and (eq_attr "tune" "cortexa5") 140 (and (eq_attr "tune" "cortexa5")
128 (eq_attr "type" "load3")) 141 (eq_attr "type" "load_12"))
129 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ 142 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
130 cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") 143 cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
131 144
132 (define_insn_reservation "cortex_a5_store4" 0 145 (define_insn_reservation "cortex_a5_store4" 0
133 (and (eq_attr "tune" "cortexa5") 146 (and (eq_attr "tune" "cortexa5")
134 (eq_attr "type" "store3")) 147 (eq_attr "type" "store_12"))
135 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ 148 "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
136 cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") 149 cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
137 150
138 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 151 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
139 ;; Branches. 152 ;; Branches.
153 ;; Floating-point arithmetic. 166 ;; Floating-point arithmetic.
154 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 167 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
155 168
156 (define_insn_reservation "cortex_a5_fpalu" 4 169 (define_insn_reservation "cortex_a5_fpalu" 4
157 (and (eq_attr "tune" "cortexa5") 170 (and (eq_attr "tune" "cortexa5")
158 (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ 171 (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, fmuls,\
172 f_cvt,f_cvtf2i,f_cvti2f,\
159 fcmps, fcmpd")) 173 fcmps, fcmpd"))
160 "cortex_a5_ex1+cortex_a5_fpadd_pipe") 174 "cortex_a5_ex1+cortex_a5_fpadd_pipe")
161 175
162 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from 176 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
163 ;; f1 to f3 (which I think reduces the latency by one cycle). 177 ;; f1 to f3 (which I think reduces the latency by one cycle).
183 ;; block other instructions attempting to use it simultaneously. We try to 197 ;; block other instructions attempting to use it simultaneously. We try to
184 ;; avoid that using cortex_a5_fpadd_pipe. 198 ;; avoid that using cortex_a5_fpadd_pipe.
185 199
186 (define_insn_reservation "cortex_a5_fpmacs" 8 200 (define_insn_reservation "cortex_a5_fpmacs" 8
187 (and (eq_attr "tune" "cortexa5") 201 (and (eq_attr "tune" "cortexa5")
188 (eq_attr "type" "fmacs")) 202 (eq_attr "type" "fmacs,ffmas"))
189 "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") 203 "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
190 204
191 ;; Non-multiply instructions can issue in the middle two instructions of a 205 ;; Non-multiply instructions can issue in the middle two instructions of a
192 ;; double-precision multiply. Note that it isn't entirely clear when a branch 206 ;; double-precision multiply. Note that it isn't entirely clear when a branch
193 ;; can dual-issue when a multi-cycle multiplication is in progress; we ignore 207 ;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
199 "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ 213 "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
200 cortex_a5_ex1+cortex_a5_fpmul_pipe") 214 cortex_a5_ex1+cortex_a5_fpmul_pipe")
201 215
202 (define_insn_reservation "cortex_a5_fpmacd" 11 216 (define_insn_reservation "cortex_a5_fpmacd" 11
203 (and (eq_attr "tune" "cortexa5") 217 (and (eq_attr "tune" "cortexa5")
204 (eq_attr "type" "fmacd")) 218 (eq_attr "type" "fmacd,ffmad"))
205 "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ 219 "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
206 cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") 220 cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
207 221
208 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 222 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
209 ;; Floating-point divide/square root instructions. 223 ;; Floating-point divide/square root instructions.
217 ;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the 231 ;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
218 ;; multiply pipeline to collect the divide/square-root result. 232 ;; multiply pipeline to collect the divide/square-root result.
219 233
220 (define_insn_reservation "cortex_a5_fdivs" 14 234 (define_insn_reservation "cortex_a5_fdivs" 14
221 (and (eq_attr "tune" "cortexa5") 235 (and (eq_attr "tune" "cortexa5")
222 (eq_attr "type" "fdivs")) 236 (eq_attr "type" "fdivs, fsqrts"))
223 "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13") 237 "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
224 238
225 ;; ??? Similarly for fdivd. 239 ;; ??? Similarly for fdivd.
226 240
227 (define_insn_reservation "cortex_a5_fdivd" 29 241 (define_insn_reservation "cortex_a5_fdivd" 29
228 (and (eq_attr "tune" "cortexa5") 242 (and (eq_attr "tune" "cortexa5")
229 (eq_attr "type" "fdivd")) 243 (eq_attr "type" "fdivd, fsqrtd"))
230 "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28") 244 "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
231 245
232 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 246 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
233 ;; VFP to/from core transfers. 247 ;; VFP to/from core transfers.
234 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 248 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
237 251
238 ;; Core-to-VFP transfers use the multiply pipeline. 252 ;; Core-to-VFP transfers use the multiply pipeline.
239 253
240 (define_insn_reservation "cortex_a5_r2f" 4 254 (define_insn_reservation "cortex_a5_r2f" 4
241 (and (eq_attr "tune" "cortexa5") 255 (and (eq_attr "tune" "cortexa5")
242 (eq_attr "type" "r_2_f")) 256 (eq_attr "type" "f_mcr,f_mcrr"))
243 "cortex_a5_ex1") 257 "cortex_a5_ex1")
244 258
245 (define_insn_reservation "cortex_a5_f2r" 2 259 (define_insn_reservation "cortex_a5_f2r" 2
246 (and (eq_attr "tune" "cortexa5") 260 (and (eq_attr "tune" "cortexa5")
247 (eq_attr "type" "f_2_r")) 261 (eq_attr "type" "f_mrc,f_mrrc"))
248 "cortex_a5_ex1") 262 "cortex_a5_ex1")
249 263
250 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 264 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
251 ;; VFP flag transfer. 265 ;; VFP flag transfer.
252 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 266 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;