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comparison gcc/config/arm/fa526.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 561a7518be6b
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Faraday FA526 Pipeline Description 1 ;; Faraday FA526 Pipeline Description
2 ;; Copyright (C) 2010 Free Software Foundation, Inc. 2 ;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. 3 ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description.
4 4
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it under 7 ;; GCC is free software; you can redistribute it and/or modify it under
52 ;; ALU Instructions 52 ;; ALU Instructions
53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
54 54
55 ;; ALU instructions require two cycles to execute, and use the ALU 55 ;; ALU instructions require two cycles to execute, and use the ALU
56 ;; pipeline in each of the three stages. The results are available 56 ;; pipeline in each of the three stages. The results are available
57 ;; after the execute stage stage has finished. 57 ;; after the execute stage has finished.
58 ;; 58 ;;
59 ;; If the destination register is the PC, the pipelines are stalled 59 ;; If the destination register is the PC, the pipelines are stalled
60 ;; for several cycles. That case is not modeled here. 60 ;; for several cycles. That case is not modeled here.
61 61
62 ;; ALU operations 62 ;; ALU operations
63 (define_insn_reservation "526_alu_op" 1 63 (define_insn_reservation "526_alu_op" 1
64 (and (eq_attr "tune" "fa526") 64 (and (eq_attr "tune" "fa526")
65 (eq_attr "type" "alu")) 65 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
66 alu_sreg,alus_sreg,logic_reg,logics_reg,\
67 adc_imm,adcs_imm,adc_reg,adcs_reg,\
68 adr,bfm,rev,\
69 shift_imm,shift_reg,\
70 mov_imm,mov_reg,mvn_imm,mvn_reg,\
71 mrs,multiple,no_insn"))
66 "fa526_core") 72 "fa526_core")
67 73
68 (define_insn_reservation "526_alu_shift_op" 2 74 (define_insn_reservation "526_alu_shift_op" 2
69 (and (eq_attr "tune" "fa526") 75 (and (eq_attr "tune" "fa526")
70 (eq_attr "type" "alu_shift,alu_shift_reg")) 76 (eq_attr "type" "extend,\
77 alu_shift_imm,alus_shift_imm,\
78 logic_shift_imm,logics_shift_imm,\
79 alu_shift_reg,alus_shift_reg,\
80 logic_shift_reg,logics_shift_reg,\
81 mov_shift,mov_shift_reg,\
82 mvn_shift,mvn_shift_reg"))
71 "fa526_core") 83 "fa526_core")
72 84
73 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 85 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
74 ;; Multiplication Instructions 86 ;; Multiplication Instructions
75 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 87 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
76 88
77 (define_insn_reservation "526_mult1" 2 89 (define_insn_reservation "526_mult1" 2
78 (and (eq_attr "tune" "fa526") 90 (and (eq_attr "tune" "fa526")
79 (eq_attr "insn" "smlalxy,smulxy,smlaxy,smlalxy")) 91 (eq_attr "type" "smlalxy,smulxy,smlaxy,smlalxy"))
80 "fa526_core") 92 "fa526_core")
81 93
82 (define_insn_reservation "526_mult2" 5 94 (define_insn_reservation "526_mult2" 5
83 (and (eq_attr "tune" "fa526") 95 (and (eq_attr "tune" "fa526")
84 (eq_attr "insn" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\ 96 (eq_attr "type" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\
85 umlals,smulls,smlals,smlawx")) 97 umlals,smulls,smlals,smlawx"))
86 "fa526_core*4") 98 "fa526_core*4")
87 99
88 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 100 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
89 ;; Load/Store Instructions 101 ;; Load/Store Instructions
94 ;; (such as "ldm!"). These models assume that all memory references 106 ;; (such as "ldm!"). These models assume that all memory references
95 ;; hit in dcache. 107 ;; hit in dcache.
96 108
97 (define_insn_reservation "526_load1_op" 3 109 (define_insn_reservation "526_load1_op" 3
98 (and (eq_attr "tune" "fa526") 110 (and (eq_attr "tune" "fa526")
99 (eq_attr "type" "load1,load_byte")) 111 (eq_attr "type" "load_4,load_byte"))
100 "fa526_core") 112 "fa526_core")
101 113
102 (define_insn_reservation "526_load2_op" 4 114 (define_insn_reservation "526_load2_op" 4
103 (and (eq_attr "tune" "fa526") 115 (and (eq_attr "tune" "fa526")
104 (eq_attr "type" "load2")) 116 (eq_attr "type" "load_8"))
105 "fa526_core*2") 117 "fa526_core*2")
106 118
107 (define_insn_reservation "526_load3_op" 5 119 (define_insn_reservation "526_load3_op" 5
108 (and (eq_attr "tune" "fa526") 120 (and (eq_attr "tune" "fa526")
109 (eq_attr "type" "load3")) 121 (eq_attr "type" "load_12"))
110 "fa526_core*3") 122 "fa526_core*3")
111 123
112 (define_insn_reservation "526_load4_op" 6 124 (define_insn_reservation "526_load4_op" 6
113 (and (eq_attr "tune" "fa526") 125 (and (eq_attr "tune" "fa526")
114 (eq_attr "type" "load4")) 126 (eq_attr "type" "load_16"))
115 "fa526_core*4") 127 "fa526_core*4")
116 128
117 (define_insn_reservation "526_store1_op" 0 129 (define_insn_reservation "526_store1_op" 0
118 (and (eq_attr "tune" "fa526") 130 (and (eq_attr "tune" "fa526")
119 (eq_attr "type" "store1")) 131 (eq_attr "type" "store_4"))
120 "fa526_core") 132 "fa526_core")
121 133
122 (define_insn_reservation "526_store2_op" 1 134 (define_insn_reservation "526_store2_op" 1
123 (and (eq_attr "tune" "fa526") 135 (and (eq_attr "tune" "fa526")
124 (eq_attr "type" "store2")) 136 (eq_attr "type" "store_8"))
125 "fa526_core*2") 137 "fa526_core*2")
126 138
127 (define_insn_reservation "526_store3_op" 2 139 (define_insn_reservation "526_store3_op" 2
128 (and (eq_attr "tune" "fa526") 140 (and (eq_attr "tune" "fa526")
129 (eq_attr "type" "store3")) 141 (eq_attr "type" "store_12"))
130 "fa526_core*3") 142 "fa526_core*3")
131 143
132 (define_insn_reservation "526_store4_op" 3 144 (define_insn_reservation "526_store4_op" 3
133 (and (eq_attr "tune" "fa526") 145 (and (eq_attr "tune" "fa526")
134 (eq_attr "type" "store4")) 146 (eq_attr "type" "store_16"))
135 "fa526_core*4") 147 "fa526_core*4")
136 148
137 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 149 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
138 ;; Branch and Call Instructions 150 ;; Branch and Call Instructions
139 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 151 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;