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comparison gcc/config/arm/iwmmxt2.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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68:561a7518be6b 111:04ced10e8804
1 ;; Patterns for the Intel Wireless MMX technology architecture.
2 ;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
3 ;; Written by Marvell, Inc.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
11
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21 (define_insn "iwmmxt_wabs<mode>3"
22 [(set (match_operand:VMMX 0 "register_operand" "=y")
23 (unspec:VMMX [(match_operand:VMMX 1 "register_operand" "y")] UNSPEC_WABS))]
24 "TARGET_REALLY_IWMMXT"
25 "wabs<MMX_char>%?\\t%0, %1"
26 [(set_attr "predicable" "yes")
27 (set_attr "type" "wmmx_wabs")]
28 )
29
30 (define_insn "iwmmxt_wabsdiffb"
31 [(set (match_operand:V8QI 0 "register_operand" "=y")
32 (truncate:V8QI
33 (abs:V8HI
34 (minus:V8HI
35 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
36 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))))))]
37 "TARGET_REALLY_IWMMXT"
38 "wabsdiffb%?\\t%0, %1, %2"
39 [(set_attr "predicable" "yes")
40 (set_attr "type" "wmmx_wabsdiff")]
41 )
42
43 (define_insn "iwmmxt_wabsdiffh"
44 [(set (match_operand:V4HI 0 "register_operand" "=y")
45 (truncate: V4HI
46 (abs:V4SI
47 (minus:V4SI
48 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
49 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))))))]
50 "TARGET_REALLY_IWMMXT"
51 "wabsdiffh%?\\t%0, %1, %2"
52 [(set_attr "predicable" "yes")
53 (set_attr "type" "wmmx_wabsdiff")]
54 )
55
56 (define_insn "iwmmxt_wabsdiffw"
57 [(set (match_operand:V2SI 0 "register_operand" "=y")
58 (truncate: V2SI
59 (abs:V2DI
60 (minus:V2DI
61 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
62 (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y"))))))]
63 "TARGET_REALLY_IWMMXT"
64 "wabsdiffw%?\\t%0, %1, %2"
65 [(set_attr "predicable" "yes")
66 (set_attr "type" "wmmx_wabsdiff")]
67 )
68
69 (define_insn "iwmmxt_waddsubhx"
70 [(set (match_operand:V4HI 0 "register_operand" "=y")
71 (vec_merge:V4HI
72 (ss_minus:V4HI
73 (match_operand:V4HI 1 "register_operand" "y")
74 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
75 (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
76 (ss_plus:V4HI
77 (match_dup 1)
78 (vec_select:V4HI (match_dup 2)
79 (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
80 (const_int 10)))]
81 "TARGET_REALLY_IWMMXT"
82 "waddsubhx%?\\t%0, %1, %2"
83 [(set_attr "predicable" "yes")
84 (set_attr "type" "wmmx_waddsubhx")]
85 )
86
87 (define_insn "iwmmxt_wsubaddhx"
88 [(set (match_operand:V4HI 0 "register_operand" "=y")
89 (vec_merge:V4HI
90 (ss_plus:V4HI
91 (match_operand:V4HI 1 "register_operand" "y")
92 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
93 (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
94 (ss_minus:V4HI
95 (match_dup 1)
96 (vec_select:V4HI (match_dup 2)
97 (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
98 (const_int 10)))]
99 "TARGET_REALLY_IWMMXT"
100 "wsubaddhx%?\\t%0, %1, %2"
101 [(set_attr "predicable" "yes")
102 (set_attr "type" "wmmx_wsubaddhx")]
103 )
104
105 (define_insn "addc<mode>3"
106 [(set (match_operand:VMMX2 0 "register_operand" "=y")
107 (unspec:VMMX2
108 [(plus:VMMX2
109 (match_operand:VMMX2 1 "register_operand" "y")
110 (match_operand:VMMX2 2 "register_operand" "y"))] UNSPEC_WADDC))]
111 "TARGET_REALLY_IWMMXT"
112 "wadd<MMX_char>c%?\\t%0, %1, %2"
113 [(set_attr "predicable" "yes")
114 (set_attr "type" "wmmx_wadd")]
115 )
116
117 (define_insn "iwmmxt_avg4"
118 [(set (match_operand:V8QI 0 "register_operand" "=y")
119 (truncate:V8QI
120 (vec_select:V8HI
121 (vec_merge:V8HI
122 (lshiftrt:V8HI
123 (plus:V8HI
124 (plus:V8HI
125 (plus:V8HI
126 (plus:V8HI
127 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
128 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
129 (vec_select:V8HI (zero_extend:V8HI (match_dup 1))
130 (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
131 (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
132 (vec_select:V8HI (zero_extend:V8HI (match_dup 2))
133 (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
134 (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
135 (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1)
136 (const_int 1) (const_int 1) (const_int 1) (const_int 1)]))
137 (const_int 2))
138 (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)
139 (const_int 0) (const_int 0) (const_int 0) (const_int 0)])
140 (const_int 254))
141 (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4)
142 (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))]
143 "TARGET_REALLY_IWMMXT"
144 "wavg4%?\\t%0, %1, %2"
145 [(set_attr "predicable" "yes")
146 (set_attr "type" "wmmx_wavg4")]
147 )
148
149 (define_insn "iwmmxt_avg4r"
150 [(set (match_operand:V8QI 0 "register_operand" "=y")
151 (truncate:V8QI
152 (vec_select:V8HI
153 (vec_merge:V8HI
154 (lshiftrt:V8HI
155 (plus:V8HI
156 (plus:V8HI
157 (plus:V8HI
158 (plus:V8HI
159 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
160 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
161 (vec_select:V8HI (zero_extend:V8HI (match_dup 1))
162 (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
163 (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
164 (vec_select:V8HI (zero_extend:V8HI (match_dup 2))
165 (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
166 (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
167 (const_vector:V8HI [(const_int 2) (const_int 2) (const_int 2) (const_int 2)
168 (const_int 2) (const_int 2) (const_int 2) (const_int 2)]))
169 (const_int 2))
170 (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)
171 (const_int 0) (const_int 0) (const_int 0) (const_int 0)])
172 (const_int 254))
173 (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4)
174 (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))]
175 "TARGET_REALLY_IWMMXT"
176 "wavg4r%?\\t%0, %1, %2"
177 [(set_attr "predicable" "yes")
178 (set_attr "type" "wmmx_wavg4")]
179 )
180
181 (define_insn "iwmmxt_wmaddsx"
182 [(set (match_operand:V2SI 0 "register_operand" "=y")
183 (plus:V2SI
184 (mult:V2SI
185 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
186 (parallel [(const_int 1) (const_int 3)]))
187 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
188 (parallel [(const_int 0) (const_int 2)])))
189 (mult:V2SI
190 (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
191 (parallel [(const_int 0) (const_int 2)]))
192 (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
193 (parallel [(const_int 1) (const_int 3)])))))]
194 "TARGET_REALLY_IWMMXT"
195 "wmaddsx%?\\t%0, %1, %2"
196 [(set_attr "predicable" "yes")
197 (set_attr "type" "wmmx_wmadd")]
198 )
199
200 (define_insn "iwmmxt_wmaddux"
201 [(set (match_operand:V2SI 0 "register_operand" "=y")
202 (plus:V2SI
203 (mult:V2SI
204 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
205 (parallel [(const_int 1) (const_int 3)]))
206 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
207 (parallel [(const_int 0) (const_int 2)])))
208 (mult:V2SI
209 (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
210 (parallel [(const_int 0) (const_int 2)]))
211 (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
212 (parallel [(const_int 1) (const_int 3)])))))]
213 "TARGET_REALLY_IWMMXT"
214 "wmaddux%?\\t%0, %1, %2"
215 [(set_attr "predicable" "yes")
216 (set_attr "type" "wmmx_wmadd")]
217 )
218
219 (define_insn "iwmmxt_wmaddsn"
220 [(set (match_operand:V2SI 0 "register_operand" "=y")
221 (minus:V2SI
222 (mult:V2SI
223 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
224 (parallel [(const_int 0) (const_int 2)]))
225 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
226 (parallel [(const_int 0) (const_int 2)])))
227 (mult:V2SI
228 (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
229 (parallel [(const_int 1) (const_int 3)]))
230 (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
231 (parallel [(const_int 1) (const_int 3)])))))]
232 "TARGET_REALLY_IWMMXT"
233 "wmaddsn%?\\t%0, %1, %2"
234 [(set_attr "predicable" "yes")
235 (set_attr "type" "wmmx_wmadd")]
236 )
237
238 (define_insn "iwmmxt_wmaddun"
239 [(set (match_operand:V2SI 0 "register_operand" "=y")
240 (minus:V2SI
241 (mult:V2SI
242 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
243 (parallel [(const_int 0) (const_int 2)]))
244 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
245 (parallel [(const_int 0) (const_int 2)])))
246 (mult:V2SI
247 (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
248 (parallel [(const_int 1) (const_int 3)]))
249 (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
250 (parallel [(const_int 1) (const_int 3)])))))]
251 "TARGET_REALLY_IWMMXT"
252 "wmaddun%?\\t%0, %1, %2"
253 [(set_attr "predicable" "yes")
254 (set_attr "type" "wmmx_wmadd")]
255 )
256
257 (define_insn "iwmmxt_wmulwsm"
258 [(set (match_operand:V2SI 0 "register_operand" "=y")
259 (truncate:V2SI
260 (ashiftrt:V2DI
261 (mult:V2DI
262 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
263 (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
264 (const_int 32))))]
265 "TARGET_REALLY_IWMMXT"
266 "wmulwsm%?\\t%0, %1, %2"
267 [(set_attr "predicable" "yes")
268 (set_attr "type" "wmmx_wmulw")]
269 )
270
271 (define_insn "iwmmxt_wmulwum"
272 [(set (match_operand:V2SI 0 "register_operand" "=y")
273 (truncate:V2SI
274 (lshiftrt:V2DI
275 (mult:V2DI
276 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
277 (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
278 (const_int 32))))]
279 "TARGET_REALLY_IWMMXT"
280 "wmulwum%?\\t%0, %1, %2"
281 [(set_attr "predicable" "yes")
282 (set_attr "type" "wmmx_wmulw")]
283 )
284
285 (define_insn "iwmmxt_wmulsmr"
286 [(set (match_operand:V4HI 0 "register_operand" "=y")
287 (truncate:V4HI
288 (ashiftrt:V4SI
289 (plus:V4SI
290 (mult:V4SI
291 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
292 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
293 (const_vector:V4SI [(const_int 32768)
294 (const_int 32768)
295 (const_int 32768)]))
296 (const_int 16))))]
297 "TARGET_REALLY_IWMMXT"
298 "wmulsmr%?\\t%0, %1, %2"
299 [(set_attr "predicable" "yes")
300 (set_attr "type" "wmmx_wmul")]
301 )
302
303 (define_insn "iwmmxt_wmulumr"
304 [(set (match_operand:V4HI 0 "register_operand" "=y")
305 (truncate:V4HI
306 (lshiftrt:V4SI
307 (plus:V4SI
308 (mult:V4SI
309 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
310 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
311 (const_vector:V4SI [(const_int 32768)
312 (const_int 32768)
313 (const_int 32768)
314 (const_int 32768)]))
315 (const_int 16))))]
316 "TARGET_REALLY_IWMMXT"
317 "wmulumr%?\\t%0, %1, %2"
318 [(set_attr "predicable" "yes")
319 (set_attr "type" "wmmx_wmul")]
320 )
321
322 (define_insn "iwmmxt_wmulwsmr"
323 [(set (match_operand:V2SI 0 "register_operand" "=y")
324 (truncate:V2SI
325 (ashiftrt:V2DI
326 (plus:V2DI
327 (mult:V2DI
328 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
329 (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
330 (const_vector:V2DI [(const_int 2147483648)
331 (const_int 2147483648)]))
332 (const_int 32))))]
333 "TARGET_REALLY_IWMMXT"
334 "wmulwsmr%?\\t%0, %1, %2"
335 [(set_attr "predicable" "yes")
336 (set_attr "type" "wmmx_wmul")]
337 )
338
339 (define_insn "iwmmxt_wmulwumr"
340 [(set (match_operand:V2SI 0 "register_operand" "=y")
341 (truncate:V2SI
342 (lshiftrt:V2DI
343 (plus:V2DI
344 (mult:V2DI
345 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
346 (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
347 (const_vector:V2DI [(const_int 2147483648)
348 (const_int 2147483648)]))
349 (const_int 32))))]
350 "TARGET_REALLY_IWMMXT"
351 "wmulwumr%?\\t%0, %1, %2"
352 [(set_attr "predicable" "yes")
353 (set_attr "type" "wmmx_wmulw")]
354 )
355
356 (define_insn "iwmmxt_wmulwl"
357 [(set (match_operand:V2SI 0 "register_operand" "=y")
358 (mult:V2SI
359 (match_operand:V2SI 1 "register_operand" "y")
360 (match_operand:V2SI 2 "register_operand" "y")))]
361 "TARGET_REALLY_IWMMXT"
362 "wmulwl%?\\t%0, %1, %2"
363 [(set_attr "predicable" "yes")
364 (set_attr "type" "wmmx_wmulw")]
365 )
366
367 (define_insn "iwmmxt_wqmulm"
368 [(set (match_operand:V4HI 0 "register_operand" "=y")
369 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
370 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULM))]
371 "TARGET_REALLY_IWMMXT"
372 "wqmulm%?\\t%0, %1, %2"
373 [(set_attr "predicable" "yes")
374 (set_attr "type" "wmmx_wqmulm")]
375 )
376
377 (define_insn "iwmmxt_wqmulwm"
378 [(set (match_operand:V2SI 0 "register_operand" "=y")
379 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y")
380 (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWM))]
381 "TARGET_REALLY_IWMMXT"
382 "wqmulwm%?\\t%0, %1, %2"
383 [(set_attr "predicable" "yes")
384 (set_attr "type" "wmmx_wqmulwm")]
385 )
386
387 (define_insn "iwmmxt_wqmulmr"
388 [(set (match_operand:V4HI 0 "register_operand" "=y")
389 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
390 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULMR))]
391 "TARGET_REALLY_IWMMXT"
392 "wqmulmr%?\\t%0, %1, %2"
393 [(set_attr "predicable" "yes")
394 (set_attr "type" "wmmx_wqmulm")]
395 )
396
397 (define_insn "iwmmxt_wqmulwmr"
398 [(set (match_operand:V2SI 0 "register_operand" "=y")
399 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y")
400 (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWMR))]
401 "TARGET_REALLY_IWMMXT"
402 "wqmulwmr%?\\t%0, %1, %2"
403 [(set_attr "predicable" "yes")
404 (set_attr "type" "wmmx_wqmulwm")]
405 )
406
407 (define_insn "iwmmxt_waddbhusm"
408 [(set (match_operand:V8QI 0 "register_operand" "=y")
409 (vec_concat:V8QI
410 (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])
411 (us_truncate:V4QI
412 (ss_plus:V4HI
413 (match_operand:V4HI 1 "register_operand" "y")
414 (zero_extend:V4HI
415 (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y")
416 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)])))))))]
417 "TARGET_REALLY_IWMMXT"
418 "waddbhusm%?\\t%0, %1, %2"
419 [(set_attr "predicable" "yes")
420 (set_attr "type" "wmmx_waddbhus")]
421 )
422
423 (define_insn "iwmmxt_waddbhusl"
424 [(set (match_operand:V8QI 0 "register_operand" "=y")
425 (vec_concat:V8QI
426 (us_truncate:V4QI
427 (ss_plus:V4HI
428 (match_operand:V4HI 1 "register_operand" "y")
429 (zero_extend:V4HI
430 (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y")
431 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))))
432 (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])))]
433 "TARGET_REALLY_IWMMXT"
434 "waddbhusl%?\\t%0, %1, %2"
435 [(set_attr "predicable" "yes")
436 (set_attr "type" "wmmx_waddbhus")]
437 )
438
439 (define_insn "iwmmxt_wqmiabb"
440 [(set (match_operand:V2SI 0 "register_operand" "=y")
441 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0")
442 (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
443 (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
444 (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
445 (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))]
446 "TARGET_REALLY_IWMMXT"
447 "wqmiabb%?\\t%0, %2, %3"
448 [(set_attr "predicable" "yes")
449 (set_attr "type" "wmmx_wqmiaxy")]
450 )
451
452 (define_insn "iwmmxt_wqmiabt"
453 [(set (match_operand:V2SI 0 "register_operand" "=y")
454 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0")
455 (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
456 (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
457 (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
458 (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))]
459 "TARGET_REALLY_IWMMXT"
460 "wqmiabt%?\\t%0, %2, %3"
461 [(set_attr "predicable" "yes")
462 (set_attr "type" "wmmx_wqmiaxy")]
463 )
464
465 (define_insn "iwmmxt_wqmiatb"
466 [(set (match_operand:V2SI 0 "register_operand" "=y")
467 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0")
468 (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
469 (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
470 (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
471 (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))]
472 "TARGET_REALLY_IWMMXT"
473 "wqmiatb%?\\t%0, %2, %3"
474 [(set_attr "predicable" "yes")
475 (set_attr "type" "wmmx_wqmiaxy")]
476 )
477
478 (define_insn "iwmmxt_wqmiatt"
479 [(set (match_operand:V2SI 0 "register_operand" "=y")
480 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0")
481 (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
482 (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
483 (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
484 (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))]
485 "TARGET_REALLY_IWMMXT"
486 "wqmiatt%?\\t%0, %2, %3"
487 [(set_attr "predicable" "yes")
488 (set_attr "type" "wmmx_wqmiaxy")]
489 )
490
491 (define_insn "iwmmxt_wqmiabbn"
492 [(set (match_operand:V2SI 0 "register_operand" "=y")
493 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0")
494 (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
495 (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
496 (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
497 (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))]
498 "TARGET_REALLY_IWMMXT"
499 "wqmiabbn%?\\t%0, %2, %3"
500 [(set_attr "predicable" "yes")
501 (set_attr "type" "wmmx_wqmiaxy")]
502 )
503
504 (define_insn "iwmmxt_wqmiabtn"
505 [(set (match_operand:V2SI 0 "register_operand" "=y")
506 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0")
507 (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
508 (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
509 (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
510 (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))]
511 "TARGET_REALLY_IWMMXT"
512 "wqmiabtn%?\\t%0, %2, %3"
513 [(set_attr "predicable" "yes")
514 (set_attr "type" "wmmx_wqmiaxy")]
515 )
516
517 (define_insn "iwmmxt_wqmiatbn"
518 [(set (match_operand:V2SI 0 "register_operand" "=y")
519 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0")
520 (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
521 (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
522 (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
523 (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))]
524 "TARGET_REALLY_IWMMXT"
525 "wqmiatbn%?\\t%0, %2, %3"
526 [(set_attr "predicable" "yes")
527 (set_attr "type" "wmmx_wqmiaxy")]
528 )
529
530 (define_insn "iwmmxt_wqmiattn"
531 [(set (match_operand:V2SI 0 "register_operand" "=y")
532 (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "0")
533 (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
534 (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
535 (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
536 (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))]
537 "TARGET_REALLY_IWMMXT"
538 "wqmiattn%?\\t%0, %2, %3"
539 [(set_attr "predicable" "yes")
540 (set_attr "type" "wmmx_wqmiaxy")]
541 )
542
543 (define_insn "iwmmxt_wmiabb"
544 [(set (match_operand:DI 0 "register_operand" "=y")
545 (plus:DI (match_operand:DI 1 "register_operand" "0")
546 (plus:DI
547 (mult:DI
548 (sign_extend:DI
549 (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
550 (parallel [(const_int 0)])))
551 (sign_extend:DI
552 (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
553 (parallel [(const_int 0)]))))
554 (mult:DI
555 (sign_extend:DI
556 (vec_select:HI (match_dup 2)
557 (parallel [(const_int 2)])))
558 (sign_extend:DI
559 (vec_select:HI (match_dup 3)
560 (parallel [(const_int 2)])))))))]
561 "TARGET_REALLY_IWMMXT"
562 "wmiabb%?\\t%0, %2, %3"
563 [(set_attr "predicable" "yes")
564 (set_attr "type" "wmmx_wmiaxy")]
565 )
566
567 (define_insn "iwmmxt_wmiabt"
568 [(set (match_operand:DI 0 "register_operand" "=y")
569 (plus:DI (match_operand:DI 1 "register_operand" "0")
570 (plus:DI
571 (mult:DI
572 (sign_extend:DI
573 (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
574 (parallel [(const_int 0)])))
575 (sign_extend:DI
576 (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
577 (parallel [(const_int 1)]))))
578 (mult:DI
579 (sign_extend:DI
580 (vec_select:HI (match_dup 2)
581 (parallel [(const_int 2)])))
582 (sign_extend:DI
583 (vec_select:HI (match_dup 3)
584 (parallel [(const_int 3)])))))))]
585 "TARGET_REALLY_IWMMXT"
586 "wmiabt%?\\t%0, %2, %3"
587 [(set_attr "predicable" "yes")
588 (set_attr "type" "wmmx_wmiaxy")]
589 )
590
591 (define_insn "iwmmxt_wmiatb"
592 [(set (match_operand:DI 0 "register_operand" "=y")
593 (plus:DI (match_operand:DI 1 "register_operand" "0")
594 (plus:DI
595 (mult:DI
596 (sign_extend:DI
597 (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
598 (parallel [(const_int 1)])))
599 (sign_extend:DI
600 (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
601 (parallel [(const_int 0)]))))
602 (mult:DI
603 (sign_extend:DI
604 (vec_select:HI (match_dup 2)
605 (parallel [(const_int 3)])))
606 (sign_extend:DI
607 (vec_select:HI (match_dup 3)
608 (parallel [(const_int 2)])))))))]
609 "TARGET_REALLY_IWMMXT"
610 "wmiatb%?\\t%0, %2, %3"
611 [(set_attr "predicable" "yes")
612 (set_attr "type" "wmmx_wmiaxy")]
613 )
614
615 (define_insn "iwmmxt_wmiatt"
616 [(set (match_operand:DI 0 "register_operand" "=y")
617 (plus:DI (match_operand:DI 1 "register_operand" "0")
618 (plus:DI
619 (mult:DI
620 (sign_extend:DI
621 (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
622 (parallel [(const_int 1)])))
623 (sign_extend:DI
624 (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
625 (parallel [(const_int 1)]))))
626 (mult:DI
627 (sign_extend:DI
628 (vec_select:HI (match_dup 2)
629 (parallel [(const_int 3)])))
630 (sign_extend:DI
631 (vec_select:HI (match_dup 3)
632 (parallel [(const_int 3)])))))))]
633 "TARGET_REALLY_IWMMXT"
634 "wmiatt%?\\t%0, %2, %3"
635 [(set_attr "predicable" "yes")
636 (set_attr "type" "wmmx_wmiaxy")]
637 )
638
639 (define_insn "iwmmxt_wmiabbn"
640 [(set (match_operand:DI 0 "register_operand" "=y")
641 (minus:DI (match_operand:DI 1 "register_operand" "0")
642 (plus:DI
643 (mult:DI
644 (sign_extend:DI
645 (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
646 (parallel [(const_int 0)])))
647 (sign_extend:DI
648 (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
649 (parallel [(const_int 0)]))))
650 (mult:DI
651 (sign_extend:DI
652 (vec_select:HI (match_dup 2)
653 (parallel [(const_int 2)])))
654 (sign_extend:DI
655 (vec_select:HI (match_dup 3)
656 (parallel [(const_int 2)])))))))]
657 "TARGET_REALLY_IWMMXT"
658 "wmiabbn%?\\t%0, %2, %3"
659 [(set_attr "predicable" "yes")
660 (set_attr "type" "wmmx_wmiaxy")]
661 )
662
663 (define_insn "iwmmxt_wmiabtn"
664 [(set (match_operand:DI 0 "register_operand" "=y")
665 (minus:DI (match_operand:DI 1 "register_operand" "0")
666 (plus:DI
667 (mult:DI
668 (sign_extend:DI
669 (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
670 (parallel [(const_int 0)])))
671 (sign_extend:DI
672 (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
673 (parallel [(const_int 1)]))))
674 (mult:DI
675 (sign_extend:DI
676 (vec_select:HI (match_dup 2)
677 (parallel [(const_int 2)])))
678 (sign_extend:DI
679 (vec_select:HI (match_dup 3)
680 (parallel [(const_int 3)])))))))]
681 "TARGET_REALLY_IWMMXT"
682 "wmiabtn%?\\t%0, %2, %3"
683 [(set_attr "predicable" "yes")
684 (set_attr "type" "wmmx_wmiaxy")]
685 )
686
687 (define_insn "iwmmxt_wmiatbn"
688 [(set (match_operand:DI 0 "register_operand" "=y")
689 (minus:DI (match_operand:DI 1 "register_operand" "0")
690 (plus:DI
691 (mult:DI
692 (sign_extend:DI
693 (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
694 (parallel [(const_int 1)])))
695 (sign_extend:DI
696 (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
697 (parallel [(const_int 0)]))))
698 (mult:DI
699 (sign_extend:DI
700 (vec_select:HI (match_dup 2)
701 (parallel [(const_int 3)])))
702 (sign_extend:DI
703 (vec_select:HI (match_dup 3)
704 (parallel [(const_int 2)])))))))]
705 "TARGET_REALLY_IWMMXT"
706 "wmiatbn%?\\t%0, %2, %3"
707 [(set_attr "predicable" "yes")
708 (set_attr "type" "wmmx_wmiaxy")]
709 )
710
711 (define_insn "iwmmxt_wmiattn"
712 [(set (match_operand:DI 0 "register_operand" "=y")
713 (minus:DI (match_operand:DI 1 "register_operand" "0")
714 (plus:DI
715 (mult:DI
716 (sign_extend:DI
717 (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
718 (parallel [(const_int 1)])))
719 (sign_extend:DI
720 (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
721 (parallel [(const_int 1)]))))
722 (mult:DI
723 (sign_extend:DI
724 (vec_select:HI (match_dup 2)
725 (parallel [(const_int 3)])))
726 (sign_extend:DI
727 (vec_select:HI (match_dup 3)
728 (parallel [(const_int 3)])))))))]
729 "TARGET_REALLY_IWMMXT"
730 "wmiattn%?\\t%0, %2, %3"
731 [(set_attr "predicable" "yes")
732 (set_attr "type" "wmmx_wmiaxy")]
733 )
734
735 (define_insn "iwmmxt_wmiawbb"
736 [(set (match_operand:DI 0 "register_operand" "=y")
737 (plus:DI
738 (match_operand:DI 1 "register_operand" "0")
739 (mult:DI
740 (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
741 (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
742 "TARGET_REALLY_IWMMXT"
743 "wmiawbb%?\\t%0, %2, %3"
744 [(set_attr "predicable" "yes")
745 (set_attr "type" "wmmx_wmiawxy")]
746 )
747
748 (define_insn "iwmmxt_wmiawbt"
749 [(set (match_operand:DI 0 "register_operand" "=y")
750 (plus:DI
751 (match_operand:DI 1 "register_operand" "0")
752 (mult:DI
753 (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
754 (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
755 "TARGET_REALLY_IWMMXT"
756 "wmiawbt%?\\t%0, %2, %3"
757 [(set_attr "predicable" "yes")
758 (set_attr "type" "wmmx_wmiawxy")]
759 )
760
761 (define_insn "iwmmxt_wmiawtb"
762 [(set (match_operand:DI 0 "register_operand" "=y")
763 (plus:DI
764 (match_operand:DI 1 "register_operand" "0")
765 (mult:DI
766 (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
767 (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
768 "TARGET_REALLY_IWMMXT"
769 "wmiawtb%?\\t%0, %2, %3"
770 [(set_attr "predicable" "yes")
771 (set_attr "type" "wmmx_wmiawxy")]
772 )
773
774 (define_insn "iwmmxt_wmiawtt"
775 [(set (match_operand:DI 0 "register_operand" "=y")
776 (plus:DI
777 (match_operand:DI 1 "register_operand" "0")
778 (mult:DI
779 (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
780 (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
781 "TARGET_REALLY_IWMMXT"
782 "wmiawtt%?\\t%0, %2, %3"
783 [(set_attr "predicable" "yes")
784 (set_attr "type" "wmmx_wmiawxy")]
785 )
786
787 (define_insn "iwmmxt_wmiawbbn"
788 [(set (match_operand:DI 0 "register_operand" "=y")
789 (minus:DI
790 (match_operand:DI 1 "register_operand" "0")
791 (mult:DI
792 (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
793 (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
794 "TARGET_REALLY_IWMMXT"
795 "wmiawbbn%?\\t%0, %2, %3"
796 [(set_attr "predicable" "yes")
797 (set_attr "type" "wmmx_wmiawxy")]
798 )
799
800 (define_insn "iwmmxt_wmiawbtn"
801 [(set (match_operand:DI 0 "register_operand" "=y")
802 (minus:DI
803 (match_operand:DI 1 "register_operand" "0")
804 (mult:DI
805 (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
806 (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
807 "TARGET_REALLY_IWMMXT"
808 "wmiawbtn%?\\t%0, %2, %3"
809 [(set_attr "predicable" "yes")
810 (set_attr "type" "wmmx_wmiawxy")]
811 )
812
813 (define_insn "iwmmxt_wmiawtbn"
814 [(set (match_operand:DI 0 "register_operand" "=y")
815 (minus:DI
816 (match_operand:DI 1 "register_operand" "0")
817 (mult:DI
818 (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
819 (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
820 "TARGET_REALLY_IWMMXT"
821 "wmiawtbn%?\\t%0, %2, %3"
822 [(set_attr "predicable" "yes")
823 (set_attr "type" "wmmx_wmiawxy")]
824 )
825
826 (define_insn "iwmmxt_wmiawttn"
827 [(set (match_operand:DI 0 "register_operand" "=y")
828 (minus:DI
829 (match_operand:DI 1 "register_operand" "0")
830 (mult:DI
831 (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
832 (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
833 "TARGET_REALLY_IWMMXT"
834 "wmiawttn%?\\t%0, %2, %3"
835 [(set_attr "predicable" "yes")
836 (set_attr "type" "wmmx_wmiawxy")]
837 )
838
839 (define_insn "iwmmxt_wmerge"
840 [(set (match_operand:DI 0 "register_operand" "=y")
841 (ior:DI
842 (ashift:DI
843 (match_operand:DI 2 "register_operand" "y")
844 (minus:SI
845 (const_int 64)
846 (mult:SI
847 (match_operand:SI 3 "immediate_operand" "i")
848 (const_int 8))))
849 (lshiftrt:DI
850 (ashift:DI
851 (match_operand:DI 1 "register_operand" "y")
852 (mult:SI
853 (match_dup 3)
854 (const_int 8)))
855 (mult:SI
856 (match_dup 3)
857 (const_int 8)))))]
858 "TARGET_REALLY_IWMMXT"
859 "wmerge%?\\t%0, %1, %2, %3"
860 [(set_attr "predicable" "yes")
861 (set_attr "type" "wmmx_wmerge")]
862 )
863
864 (define_insn "iwmmxt_tandc<mode>3"
865 [(set (reg:CC CC_REGNUM)
866 (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TANDC) 0))
867 (unspec:CC [(reg:SI 15)] UNSPEC_TANDC)]
868 "TARGET_REALLY_IWMMXT"
869 "tandc<MMX_char>%?\\t r15"
870 [(set_attr "predicable" "yes")
871 (set_attr "type" "wmmx_tandc")]
872 )
873
874 (define_insn "iwmmxt_torc<mode>3"
875 [(set (reg:CC CC_REGNUM)
876 (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORC) 0))
877 (unspec:CC [(reg:SI 15)] UNSPEC_TORC)]
878 "TARGET_REALLY_IWMMXT"
879 "torc<MMX_char>%?\\t r15"
880 [(set_attr "predicable" "yes")
881 (set_attr "type" "wmmx_torc")]
882 )
883
884 (define_insn "iwmmxt_torvsc<mode>3"
885 [(set (reg:CC CC_REGNUM)
886 (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORVSC) 0))
887 (unspec:CC [(reg:SI 15)] UNSPEC_TORVSC)]
888 "TARGET_REALLY_IWMMXT"
889 "torvsc<MMX_char>%?\\t r15"
890 [(set_attr "predicable" "yes")
891 (set_attr "type" "wmmx_torvsc")]
892 )
893
894 (define_insn "iwmmxt_textrc<mode>3"
895 [(set (reg:CC CC_REGNUM)
896 (subreg:CC (unspec:VMMX [(const_int 0)
897 (match_operand:SI 0 "immediate_operand" "i")] UNSPEC_TEXTRC) 0))
898 (unspec:CC [(reg:SI 15)] UNSPEC_TEXTRC)]
899 "TARGET_REALLY_IWMMXT"
900 "textrc<MMX_char>%?\\t r15, %0"
901 [(set_attr "predicable" "yes")
902 (set_attr "type" "wmmx_textrc")]
903 )