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comparison gcc/config/rs6000/e300c2c3.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 77e2b8dfacca
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Pipeline description for Motorola PowerPC e300c3 core. 1 ;; Pipeline description for Motorola PowerPC e300c3 core.
2 ;; Copyright (C) 2008, 2009 Free Software Foundation, Inc. 2 ;; Copyright (C) 2008-2017 Free Software Foundation, Inc.
3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com) 3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
81 (define_reservation "ppce300c3_iu_stage0" 81 (define_reservation "ppce300c3_iu_stage0"
82 "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0") 82 "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
83 83
84 ;; Compares can be executed either one of the IU or SRU 84 ;; Compares can be executed either one of the IU or SRU
85 (define_insn_reservation "ppce300c3_cmp" 1 85 (define_insn_reservation "ppce300c3_cmp" 1
86 (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare") 86 (and (ior (eq_attr "type" "cmp")
87 (and (eq_attr "type" "add,logical,shift,exts")
88 (eq_attr "dot" "yes")))
87 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 89 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
88 "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \ 90 "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
89 +ppce300c3_retire") 91 +ppce300c3_retire")
90 92
91 ;; Other one cycle IU insns 93 ;; Other one cycle IU insns
92 (define_insn_reservation "ppce300c3_iu" 1 94 (define_insn_reservation "ppce300c3_iu" 1
93 (and (eq_attr "type" "integer,insert_word,isel") 95 (and (ior (eq_attr "type" "integer,insert,isel")
96 (and (eq_attr "type" "add,logical,shift,exts")
97 (eq_attr "dot" "no")))
94 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 98 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
95 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire") 99 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
96 100
97 ;; Branch. Actually this latency time is not used by the scheduler. 101 ;; Branch. Actually this latency time is not used by the scheduler.
98 (define_insn_reservation "ppce300c3_branch" 1 102 (define_insn_reservation "ppce300c3_branch" 1
100 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 104 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
101 "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire") 105 "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
102 106
103 ;; Multiply is non-pipelined but can be executed in any IU 107 ;; Multiply is non-pipelined but can be executed in any IU
104 (define_insn_reservation "ppce300c3_multiply" 2 108 (define_insn_reservation "ppce300c3_multiply" 2
105 (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 109 (and (eq_attr "type" "mul")
106 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 110 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
107 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \ 111 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
108 ppce300c3_iu_stage0+ppce300c3_retire") 112 ppce300c3_iu_stage0+ppce300c3_retire")
109 113
110 ;; Divide. We use the average latency time here. We omit reserving a 114 ;; Divide. We use the average latency time here. We omit reserving a
111 ;; retire unit because of the result automata will be huge. 115 ;; retire unit because of the result automata will be huge.
112 (define_insn_reservation "ppce300c3_divide" 20 116 (define_insn_reservation "ppce300c3_divide" 20
113 (and (eq_attr "type" "idiv") 117 (and (eq_attr "type" "div")
114 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 118 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
115 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\ 119 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
116 ppce300c3_mu_div*19") 120 ppce300c3_mu_div*19")
117 121
118 ;; CR logical 122 ;; CR logical
144 (and (eq_attr "type" "fpcompare") 148 (and (eq_attr "type" "fpcompare")
145 (eq_attr "cpu" "ppce300c3")) 149 (eq_attr "cpu" "ppce300c3"))
146 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") 150 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
147 151
148 (define_insn_reservation "ppce300c3_fp" 3 152 (define_insn_reservation "ppce300c3_fp" 3
149 (and (eq_attr "type" "fp") 153 (and (eq_attr "type" "fp,fpsimple")
150 (eq_attr "cpu" "ppce300c3")) 154 (eq_attr "cpu" "ppce300c3"))
151 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") 155 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
152 156
153 (define_insn_reservation "ppce300c3_dmul" 4 157 (define_insn_reservation "ppce300c3_dmul" 4
154 (and (eq_attr "type" "dmul") 158 (and (eq_attr "type" "dmul")
166 (eq_attr "cpu" "ppce300c3")) 170 (eq_attr "cpu" "ppce300c3"))
167 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32") 171 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
168 172
169 ;; Loads 173 ;; Loads
170 (define_insn_reservation "ppce300c3_load" 2 174 (define_insn_reservation "ppce300c3_load" 2
171 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") 175 (and (eq_attr "type" "load")
172 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 176 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
173 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") 177 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
174 178
175 (define_insn_reservation "ppce300c3_fpload" 2 179 (define_insn_reservation "ppce300c3_fpload" 2
176 (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 180 (and (eq_attr "type" "fpload")
177 (eq_attr "cpu" "ppce300c3")) 181 (eq_attr "cpu" "ppce300c3"))
178 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") 182 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
179 183
180 ;; Stores. 184 ;; Stores.
181 (define_insn_reservation "ppce300c3_store" 2 185 (define_insn_reservation "ppce300c3_store" 2
182 (and (eq_attr "type" "store,store_ux,store_u") 186 (and (eq_attr "type" "store")
183 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 187 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
184 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") 188 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
185 189
186 (define_insn_reservation "ppce300c3_fpstore" 2 190 (define_insn_reservation "ppce300c3_fpstore" 2
187 (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") 191 (and (eq_attr "type" "fpstore")
188 (eq_attr "cpu" "ppce300c3")) 192 (eq_attr "cpu" "ppce300c3"))
189 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") 193 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")