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comparison gcc/config/rs6000/e300c2c3.md @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
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131:84e7813d76e9 145:1830386684a0
1 ;; Pipeline description for Motorola PowerPC e300c3 core. 1 ;; Pipeline description for Motorola PowerPC e300c3 core.
2 ;; Copyright (C) 2008-2018 Free Software Foundation, Inc. 2 ;; Copyright (C) 2008-2020 Free Software Foundation, Inc.
3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com) 3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
20 20
21 (define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire") 21 (define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
22 (define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most") 22 (define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
23 23
24 ;; We don't simulate general issue queue (GIC). If we have SU insn 24 ;; We don't simulate general issue queue (GIC). If we have SU insn
25 ;; and then SU1 insn, they can not be issued on the same cycle 25 ;; and then SU1 insn, they cannot be issued on the same cycle
26 ;; (although SU1 insn and then SU insn can be issued) because the SU 26 ;; (although SU1 insn and then SU insn can be issued) because the SU
27 ;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle 27 ;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
28 ;; multipass insn scheduling will find the situation and issue the SU1 28 ;; multipass insn scheduling will find the situation and issue the SU1
29 ;; insn and then the SU insn. 29 ;; insn and then the SU insn.
30 (define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most") 30 (define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
31 31
32 ;; We could describe completion buffers slots in combination with the 32 ;; We could describe completion buffers slots in combination with the
33 ;; retirement units and the order of completion but the result 33 ;; retirement units and the order of completion but the result
34 ;; automaton would behave in the same way because we can not describe 34 ;; automaton would behave in the same way because we cannot describe
35 ;; real latency time with taking in order completion into account. 35 ;; real latency time with taking in order completion into account.
36 ;; Actually we could define the real latency time by querying reserved 36 ;; Actually we could define the real latency time by querying reserved
37 ;; automaton units but the current scheduler uses latency time before 37 ;; automaton units but the current scheduler uses latency time before
38 ;; issuing insns and making any reservations. 38 ;; issuing insns and making any reservations.
39 ;; 39 ;;