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comparison gcc/config/rs6000/power4.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
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52:c156f1bd5cd9 55:77e2b8dfacca
1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors. 1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
2 ;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. 2 ;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify it 6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published 7 ;; under the terms of the GNU General Public License as published
39 |(du2_power4,lsu2_power4)\ 39 |(du2_power4,lsu2_power4)\
40 |(du3_power4,lsu2_power4)\ 40 |(du3_power4,lsu2_power4)\
41 |(du4_power4,lsu1_power4)") 41 |(du4_power4,lsu1_power4)")
42 42
43 (define_reservation "lsuq_power4" 43 (define_reservation "lsuq_power4"
44 "(du1_power4+du2_power4,lsu1_power4+iu2_power4)\ 44 "((du1_power4+du2_power4,lsu1_power4)\
45 |(du2_power4+du3_power4,lsu2_power4+iu2_power4)\ 45 |(du2_power4+du3_power4,lsu2_power4)\
46 |(du3_power4+du4_power4,lsu2_power4+iu1_power4)") 46 |(du3_power4+du4_power4,lsu2_power4))\
47 +(nothing,iu2_power4|nothing,iu1_power4)")
47 48
48 (define_reservation "iq_power4" 49 (define_reservation "iq_power4"
49 "(du1_power4,iu1_power4)\ 50 "(du1_power4|du2_power4|du3_power4|du4_power4),\
50 |(du2_power4,iu2_power4)\ 51 (iu1_power4|iu2_power4)")
51 |(du3_power4,iu2_power4)\
52 |(du4_power4,iu1_power4)")
53 52
54 (define_reservation "fpq_power4" 53 (define_reservation "fpq_power4"
55 "(du1_power4,fpu1_power4)\ 54 "(du1_power4|du2_power4|du3_power4|du4_power4),\
56 |(du2_power4,fpu2_power4)\ 55 (fpu1_power4|fpu2_power4)")
57 |(du3_power4,fpu2_power4)\
58 |(du4_power4,fpu1_power4)")
59 56
60 (define_reservation "vq_power4" 57 (define_reservation "vq_power4"
61 "(du1_power4,vec_power4)\ 58 "(du1_power4,vec_power4)\
62 |(du2_power4,vec_power4)\ 59 |(du2_power4,vec_power4)\
63 |(du3_power4,vec_power4)\ 60 |(du3_power4,vec_power4)\
84 "lsq_power4") 81 "lsq_power4")
85 82
86 (define_insn_reservation "power4-load-ext" 5 83 (define_insn_reservation "power4-load-ext" 5
87 (and (eq_attr "type" "load_ext") 84 (and (eq_attr "type" "load_ext")
88 (eq_attr "cpu" "power4")) 85 (eq_attr "cpu" "power4"))
89 "(du1_power4+du2_power4,lsu1_power4,nothing,nothing,iu2_power4)\ 86 "(du1_power4+du2_power4,lsu1_power4\
90 |(du2_power4+du3_power4,lsu2_power4,nothing,nothing,iu2_power4)\ 87 |du2_power4+du3_power4,lsu2_power4\
91 |(du3_power4+du4_power4,lsu2_power4,nothing,nothing,iu1_power4)") 88 |du3_power4+du4_power4,lsu2_power4),\
89 nothing,nothing,\
90 (iu2_power4|iu1_power4)")
92 91
93 (define_insn_reservation "power4-load-ext-update" 5 92 (define_insn_reservation "power4-load-ext-update" 5
94 (and (eq_attr "type" "load_ext_u") 93 (and (eq_attr "type" "load_ext_u")
95 (eq_attr "cpu" "power4")) 94 (eq_attr "cpu" "power4"))
96 "du1_power4+du2_power4+du3_power4+du4_power4,\ 95 "du1_power4+du2_power4+du3_power4+du4_power4,\
129 "lsq_power4") 128 "lsq_power4")
130 129
131 (define_insn_reservation "power4-store" 12 130 (define_insn_reservation "power4-store" 12
132 (and (eq_attr "type" "store") 131 (and (eq_attr "type" "store")
133 (eq_attr "cpu" "power4")) 132 (eq_attr "cpu" "power4"))
134 "(du1_power4,lsu1_power4,iu1_power4)\ 133 "((du1_power4,lsu1_power4)\
135 |(du2_power4,lsu2_power4,iu2_power4)\ 134 |(du2_power4,lsu2_power4)\
136 |(du3_power4,lsu2_power4,iu2_power4)\ 135 |(du3_power4,lsu2_power4)\
137 |(du4_power4,lsu1_power4,iu1_power4)") 136 |(du4_power4,lsu1_power4)),\
137 (iu1_power4|iu2_power4)")
138 138
139 (define_insn_reservation "power4-store-update" 12 139 (define_insn_reservation "power4-store-update" 12
140 (and (eq_attr "type" "store_u") 140 (and (eq_attr "type" "store_u")
141 (eq_attr "cpu" "power4")) 141 (eq_attr "cpu" "power4"))
142 "(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\ 142 "((du1_power4+du2_power4,lsu1_power4)\
143 |(du2_power4+du3_power4,lsu2_power4+iu2_power4,iu2_power4)\ 143 |(du2_power4+du3_power4,lsu2_power4)\
144 |(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\ 144 |(du3_power4+du4_power4,lsu2_power4)\
145 |(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)") 145 |(du3_power4+du4_power4,lsu2_power4))+\
146 ((nothing,iu2_power4,iu1_power4)\
147 |(nothing,iu2_power4,iu2_power4)\
148 |(nothing,iu1_power4,iu2_power4)\
149 |(nothing,iu1_power4,iu2_power4))")
146 150
147 (define_insn_reservation "power4-store-update-indexed" 12 151 (define_insn_reservation "power4-store-update-indexed" 12
148 (and (eq_attr "type" "store_ux") 152 (and (eq_attr "type" "store_ux")
149 (eq_attr "cpu" "power4")) 153 (eq_attr "cpu" "power4"))
150 "du1_power4+du2_power4+du3_power4+du4_power4,\ 154 "du1_power4+du2_power4+du3_power4+du4_power4,\
151 iu1_power4,lsu2_power4+iu2_power4,iu2_power4") 155 iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
152 156
153 (define_insn_reservation "power4-fpstore" 12 157 (define_insn_reservation "power4-fpstore" 12
154 (and (eq_attr "type" "fpstore") 158 (and (eq_attr "type" "fpstore")
155 (eq_attr "cpu" "power4")) 159 (eq_attr "cpu" "power4"))
156 "(du1_power4,lsu1_power4,fpu1_power4)\ 160 "((du1_power4,lsu1_power4)\
157 |(du2_power4,lsu2_power4,fpu2_power4)\ 161 |(du2_power4,lsu2_power4)\
158 |(du3_power4,lsu2_power4,fpu2_power4)\ 162 |(du3_power4,lsu2_power4)\
159 |(du4_power4,lsu1_power4,fpu1_power4)") 163 |(du4_power4,lsu1_power4)),\
164 (fpu1_power4|fpu2_power4)")
160 165
161 (define_insn_reservation "power4-fpstore-update" 12 166 (define_insn_reservation "power4-fpstore-update" 12
162 (and (eq_attr "type" "fpstore_u,fpstore_ux") 167 (and (eq_attr "type" "fpstore_u,fpstore_ux")
163 (eq_attr "cpu" "power4")) 168 (eq_attr "cpu" "power4"))
164 "(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\ 169 "((du1_power4+du2_power4,lsu1_power4)\
165 |(du2_power4+du3_power4,lsu2_power4+iu2_power4,fpu2_power4)\ 170 |(du2_power4+du3_power4,lsu2_power4)\
166 |(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)") 171 |(du3_power4+du4_power4,lsu2_power4))\
172 +(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))")
167 173
168 (define_insn_reservation "power4-vecstore" 12 174 (define_insn_reservation "power4-vecstore" 12
169 (and (eq_attr "type" "vecstore") 175 (and (eq_attr "type" "vecstore")
170 (eq_attr "cpu" "power4")) 176 (eq_attr "cpu" "power4"))
171 "(du1_power4,lsu1_power4,vec_power4)\ 177 "(du1_power4,lsu1_power4,vec_power4)\
174 |(du4_power4,lsu1_power4,vec_power4)") 180 |(du4_power4,lsu1_power4,vec_power4)")
175 181
176 (define_insn_reservation "power4-llsc" 11 182 (define_insn_reservation "power4-llsc" 11
177 (and (eq_attr "type" "load_l,store_c,sync") 183 (and (eq_attr "type" "load_l,store_c,sync")
178 (eq_attr "cpu" "power4")) 184 (eq_attr "cpu" "power4"))
179 "du1_power4+du2_power4+du3_power4+du4_power4,\ 185 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
180 lsu1_power4")
181 186
182 187
183 ; Integer latency is 2 cycles 188 ; Integer latency is 2 cycles
184 (define_insn_reservation "power4-integer" 2 189 (define_insn_reservation "power4-integer" 2
185 (and (eq_attr "type" "integer,insert_dword,shift,trap,\ 190 (and (eq_attr "type" "integer,insert_dword,shift,trap,\
186 var_shift_rotate,cntlz,exts") 191 var_shift_rotate,cntlz,exts,isel")
187 (eq_attr "cpu" "power4")) 192 (eq_attr "cpu" "power4"))
188 "iq_power4") 193 "iq_power4")
189 194
190 (define_insn_reservation "power4-two" 2 195 (define_insn_reservation "power4-two" 2
191 (and (eq_attr "type" "two") 196 (and (eq_attr "type" "two")
192 (eq_attr "cpu" "power4")) 197 (eq_attr "cpu" "power4"))
193 "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\ 198 "((du1_power4+du2_power4)\
194 |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\ 199 |(du2_power4+du3_power4)\
195 |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)\ 200 |(du3_power4+du4_power4)\
196 |(du4_power4+du1_power4,iu1_power4,nothing,iu1_power4)") 201 |(du4_power4+du1_power4)),\
202 ((iu1_power4,nothing,iu2_power4)\
203 |(iu2_power4,nothing,iu2_power4)\
204 |(iu2_power4,nothing,iu1_power4)\
205 |(iu1_power4,nothing,iu1_power4))")
197 206
198 (define_insn_reservation "power4-three" 2 207 (define_insn_reservation "power4-three" 2
199 (and (eq_attr "type" "three") 208 (and (eq_attr "type" "three")
200 (eq_attr "cpu" "power4")) 209 (eq_attr "cpu" "power4"))
201 "(du1_power4+du2_power4+du3_power4,\ 210 "(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\
202 iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\ 211 |du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\
203 |(du2_power4+du3_power4+du4_power4,\ 212 ((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
204 iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\ 213 |(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
205 |(du3_power4+du4_power4+du1_power4,\ 214 |(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
206 iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\ 215 |(iu1_power4,nothing,iu2_power4,nothing,iu2_power4))")
207 |(du4_power4+du1_power4+du2_power4,\
208 iu1_power4,nothing,iu2_power4,nothing,iu2_power4)")
209 216
210 (define_insn_reservation "power4-insert" 4 217 (define_insn_reservation "power4-insert" 4
211 (and (eq_attr "type" "insert_word") 218 (and (eq_attr "type" "insert_word")
212 (eq_attr "cpu" "power4")) 219 (eq_attr "cpu" "power4"))
213 "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\ 220 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
214 |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\ 221 ((iu1_power4,nothing,iu2_power4)\
215 |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)") 222 |(iu2_power4,nothing,iu2_power4)\
223 |(iu2_power4,nothing,iu1_power4))")
216 224
217 (define_insn_reservation "power4-cmp" 3 225 (define_insn_reservation "power4-cmp" 3
218 (and (eq_attr "type" "cmp,fast_compare") 226 (and (eq_attr "type" "cmp,fast_compare")
219 (eq_attr "cpu" "power4")) 227 (eq_attr "cpu" "power4"))
220 "iq_power4") 228 "iq_power4")
221 229
222 (define_insn_reservation "power4-compare" 2 230 (define_insn_reservation "power4-compare" 2
223 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare") 231 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
224 (eq_attr "cpu" "power4")) 232 (eq_attr "cpu" "power4"))
225 "(du1_power4+du2_power4,iu1_power4,iu2_power4)\ 233 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
226 |(du2_power4+du3_power4,iu2_power4,iu2_power4)\ 234 ((iu1_power4,iu2_power4)\
227 |(du3_power4+du4_power4,iu2_power4,iu1_power4)") 235 |(iu2_power4,iu2_power4)\
236 |(iu2_power4,iu1_power4))")
228 237
229 (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 238 (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
230 239
231 (define_insn_reservation "power4-lmul-cmp" 7 240 (define_insn_reservation "power4-lmul-cmp" 7
232 (and (eq_attr "type" "lmul_compare") 241 (and (eq_attr "type" "lmul_compare")
233 (eq_attr "cpu" "power4")) 242 (eq_attr "cpu" "power4"))
234 "(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\ 243 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
235 |(du2_power4+du3_power4,iu2_power4*6,iu2_power4)\ 244 ((iu1_power4*6,iu2_power4)\
236 |(du3_power4+du4_power4,iu2_power4*6,iu1_power4)") 245 |(iu2_power4*6,iu2_power4)\
246 |(iu2_power4*6,iu1_power4))")
237 247
238 (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 248 (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
239 249
240 (define_insn_reservation "power4-imul-cmp" 5 250 (define_insn_reservation "power4-imul-cmp" 5
241 (and (eq_attr "type" "imul_compare") 251 (and (eq_attr "type" "imul_compare")
242 (eq_attr "cpu" "power4")) 252 (eq_attr "cpu" "power4"))
243 "(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\ 253 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
244 |(du2_power4+du3_power4,iu2_power4*4,iu2_power4)\ 254 ((iu1_power4*4,iu2_power4)\
245 |(du3_power4+du4_power4,iu2_power4*4,iu1_power4)") 255 |(iu2_power4*4,iu2_power4)\
256 |(iu2_power4*4,iu1_power4))")
246 257
247 (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 258 (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
248 259
249 (define_insn_reservation "power4-lmul" 7 260 (define_insn_reservation "power4-lmul" 7
250 (and (eq_attr "type" "lmul") 261 (and (eq_attr "type" "lmul")
251 (eq_attr "cpu" "power4")) 262 (eq_attr "cpu" "power4"))
252 "(du1_power4,iu1_power4*6)\ 263 "(du1_power4|du2_power4|du3_power4|du4_power4),\
253 |(du2_power4,iu2_power4*6)\ 264 (iu1_power4*6|iu2_power4*6)")
254 |(du3_power4,iu2_power4*6)\
255 |(du4_power4,iu1_power4*6)")
256 265
257 (define_insn_reservation "power4-imul" 5 266 (define_insn_reservation "power4-imul" 5
258 (and (eq_attr "type" "imul") 267 (and (eq_attr "type" "imul")
259 (eq_attr "cpu" "power4")) 268 (eq_attr "cpu" "power4"))
260 "(du1_power4,iu1_power4*4)\ 269 "(du1_power4|du2_power4|du3_power4|du4_power4),\
261 |(du2_power4,iu2_power4*4)\ 270 (iu1_power4*4|iu2_power4*4)")
262 |(du3_power4,iu2_power4*4)\
263 |(du4_power4,iu1_power4*4)")
264 271
265 (define_insn_reservation "power4-imul3" 4 272 (define_insn_reservation "power4-imul3" 4
266 (and (eq_attr "type" "imul2,imul3") 273 (and (eq_attr "type" "imul2,imul3")
267 (eq_attr "cpu" "power4")) 274 (eq_attr "cpu" "power4"))
268 "(du1_power4,iu1_power4*3)\ 275 "(du1_power4|du2_power4|du3_power4|du4_power4),\
269 |(du2_power4,iu2_power4*3)\ 276 (iu1_power4*3|iu2_power4*3)")
270 |(du3_power4,iu2_power4*3)\
271 |(du4_power4,iu1_power4*3)")
272 277
273 278
274 ; SPR move only executes in first IU. 279 ; SPR move only executes in first IU.
275 ; Integer division only executes in second IU. 280 ; Integer division only executes in second IU.
276 (define_insn_reservation "power4-idiv" 36 281 (define_insn_reservation "power4-idiv" 36
345 "fpq_power4") 350 "fpq_power4")
346 351
347 (define_insn_reservation "power4-sdiv" 33 352 (define_insn_reservation "power4-sdiv" 33
348 (and (eq_attr "type" "sdiv,ddiv") 353 (and (eq_attr "type" "sdiv,ddiv")
349 (eq_attr "cpu" "power4")) 354 (eq_attr "cpu" "power4"))
350 "(du1_power4,fpu1_power4*28)\ 355 "(du1_power4|du2_power4|du3_power4|du4_power4),\
351 |(du2_power4,fpu2_power4*28)\ 356 (fpu1_power4*28|fpu2_power4*28)")
352 |(du3_power4,fpu2_power4*28)\
353 |(du4_power4,fpu1_power4*28)")
354 357
355 (define_insn_reservation "power4-sqrt" 40 358 (define_insn_reservation "power4-sqrt" 40
356 (and (eq_attr "type" "ssqrt,dsqrt") 359 (and (eq_attr "type" "ssqrt,dsqrt")
357 (eq_attr "cpu" "power4")) 360 (eq_attr "cpu" "power4"))
358 "(du1_power4,fpu1_power4*35)\ 361 "(du1_power4|du2_power4|du3_power4|du4_power4),\
359 |(du2_power4,fpu2_power4*35)\ 362 (fpu1_power4*35|fpu2_power4*35)")
360 |(du3_power4,fpu2_power4*35)\
361 |(du4_power4,fpu2_power4*35)")
362 363
363 (define_insn_reservation "power4-isync" 2 364 (define_insn_reservation "power4-isync" 2
364 (and (eq_attr "type" "isync") 365 (and (eq_attr "type" "isync")
365 (eq_attr "cpu" "power4")) 366 (eq_attr "cpu" "power4"))
366 "du1_power4+du2_power4+du3_power4+du4_power4,\ 367 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
367 lsu1_power4")
368 368
369 369
370 ; VMX 370 ; VMX
371 (define_insn_reservation "power4-vecsimple" 2 371 (define_insn_reservation "power4-vecsimple" 2
372 (and (eq_attr "type" "vecsimple") 372 (and (eq_attr "type" "vecsimple")