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comparison include/longlong.h @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
equal deleted inserted replaced
111:04ced10e8804 131:84e7813d76e9
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic. 1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991-2017 Free Software Foundation, Inc. 2 Copyright (C) 1991-2018 Free Software Foundation, Inc.
3 3
4 This file is part of the GNU C Library. 4 This file is part of the GNU C Library.
5 5
6 The GNU C Library is free software; you can redistribute it and/or 6 The GNU C Library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public 7 modify it under the terms of the GNU Lesser General Public
1048 (count) += 16; \ 1048 (count) += 16; \
1049 } \ 1049 } \
1050 } while (0) 1050 } while (0)
1051 #endif 1051 #endif
1052 1052
1053 #if defined(__riscv)
1054 #ifdef __riscv_mul
1055 #define __umulsidi3(u,v) ((UDWtype)(UWtype)(u) * (UWtype)(v))
1056 #define __muluw3(a, b) ((UWtype)(a) * (UWtype)(b))
1057 #else
1058 #if __riscv_xlen == 32
1059 #define MULUW3 "call __mulsi3"
1060 #elif __riscv_xlen == 64
1061 #define MULUW3 "call __muldi3"
1062 #else
1063 #error unsupport xlen
1064 #endif /* __riscv_xlen */
1065 /* We rely on the fact that MULUW3 doesn't clobber the t-registers.
1066 It can get better register allocation result. */
1067 #define __muluw3(a, b) \
1068 ({ \
1069 register UWtype __op0 asm ("a0") = a; \
1070 register UWtype __op1 asm ("a1") = b; \
1071 asm volatile (MULUW3 \
1072 : "+r" (__op0), "+r" (__op1) \
1073 : \
1074 : "ra", "a2", "a3"); \
1075 __op0; \
1076 })
1077 #endif /* __riscv_mul */
1078 #define umul_ppmm(w1, w0, u, v) \
1079 do { \
1080 UWtype __x0, __x1, __x2, __x3; \
1081 UHWtype __ul, __vl, __uh, __vh; \
1082 \
1083 __ul = __ll_lowpart (u); \
1084 __uh = __ll_highpart (u); \
1085 __vl = __ll_lowpart (v); \
1086 __vh = __ll_highpart (v); \
1087 \
1088 __x0 = __muluw3 (__ul, __vl); \
1089 __x1 = __muluw3 (__ul, __vh); \
1090 __x2 = __muluw3 (__uh, __vl); \
1091 __x3 = __muluw3 (__uh, __vh); \
1092 \
1093 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1094 __x1 += __x2; /* but this indeed can */ \
1095 if (__x1 < __x2) /* did we get it? */ \
1096 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1097 \
1098 (w1) = __x3 + __ll_highpart (__x1); \
1099 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1100 } while (0)
1101 #endif /* __riscv */
1102
1053 #if defined(__sh__) && W_TYPE_SIZE == 32 1103 #if defined(__sh__) && W_TYPE_SIZE == 32
1054 #ifndef __sh1__ 1104 #ifndef __sh1__
1055 #define umul_ppmm(w1, w0, u, v) \ 1105 #define umul_ppmm(w1, w0, u, v) \
1056 __asm__ ( \ 1106 __asm__ ( \
1057 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \ 1107 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \