--- a/gcc/config/rs6000/e300c2c3.md	Thu Oct 25 07:37:49 2018 +0900
+++ b/gcc/config/rs6000/e300c2c3.md	Thu Feb 13 11:34:05 2020 +0900
@@ -1,5 +1,5 @@
 ;; Pipeline description for Motorola PowerPC e300c3 core.
-;;   Copyright (C) 2008-2018 Free Software Foundation, Inc.
+;;   Copyright (C) 2008-2020 Free Software Foundation, Inc.
 ;;   Contributed by Edmar Wienskoski (edmar@freescale.com)
 ;;
 ;; This file is part of GCC.
@@ -22,7 +22,7 @@
 (define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
 
 ;; We don't simulate general issue queue (GIC).  If we have SU insn
-;; and then SU1 insn, they can not be issued on the same cycle
+;; and then SU1 insn, they cannot be issued on the same cycle
 ;; (although SU1 insn and then SU insn can be issued) because the SU
 ;; insn will go to SU1 from GIC0 entry.  Fortunately, the first cycle
 ;; multipass insn scheduling will find the situation and issue the SU1
@@ -31,7 +31,7 @@
 
 ;; We could describe completion buffers slots in combination with the
 ;; retirement units and the order of completion but the result
-;; automaton would behave in the same way because we can not describe
+;; automaton would behave in the same way because we cannot describe
 ;; real latency time with taking in order completion into account.
 ;; Actually we could define the real latency time by querying reserved
 ;; automaton units but the current scheduler uses latency time before