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annotate llvm/test/Transforms/CodeGenPrepare/X86/computedgoto.ll @ 173:0572611fdcc8 llvm10 llvm12

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reorgnization done
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 25 May 2020 11:55:54 +0900
parents 1d019706d866
children 1f2b6ac9f198
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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2 ; RUN: opt -codegenprepare -S < %s | FileCheck %s
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3 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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4 target triple = "x86_64-unknown-linux-gnu"
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5
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6 declare void @use(i32) local_unnamed_addr
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7 declare void @useptr([2 x i8*]*) local_unnamed_addr
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8
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9 ; CHECK: @simple.targets = constant [2 x i8*] [i8* blockaddress(@simple, %bb0), i8* blockaddress(@simple, %bb1)], align 16
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10 @simple.targets = constant [2 x i8*] [i8* blockaddress(@simple, %bb0), i8* blockaddress(@simple, %bb1)], align 16
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11
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12 ; CHECK: @multi.targets = constant [2 x i8*] [i8* blockaddress(@multi, %bb0), i8* blockaddress(@multi, %bb1)], align 16
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13 @multi.targets = constant [2 x i8*] [i8* blockaddress(@multi, %bb0), i8* blockaddress(@multi, %bb1)], align 16
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14
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15 ; CHECK: @loop.targets = constant [2 x i8*] [i8* blockaddress(@loop, %bb0), i8* blockaddress(@loop, %bb1)], align 16
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16 @loop.targets = constant [2 x i8*] [i8* blockaddress(@loop, %bb0), i8* blockaddress(@loop, %bb1)], align 16
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17
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18 ; CHECK: @nophi.targets = constant [2 x i8*] [i8* blockaddress(@nophi, %bb0), i8* blockaddress(@nophi, %bb1)], align 16
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19 @nophi.targets = constant [2 x i8*] [i8* blockaddress(@nophi, %bb0), i8* blockaddress(@nophi, %bb1)], align 16
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20
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21 ; CHECK: @noncritical.targets = constant [2 x i8*] [i8* blockaddress(@noncritical, %bb0), i8* blockaddress(@noncritical, %bb1)], align 16
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22 @noncritical.targets = constant [2 x i8*] [i8* blockaddress(@noncritical, %bb0), i8* blockaddress(@noncritical, %bb1)], align 16
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23
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24 ; Check that we break the critical edge when an jump table has only one use.
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25 define void @simple(i32* nocapture readonly %p) {
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26 ; CHECK-LABEL: @simple(
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27 ; CHECK-NEXT: entry:
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28 ; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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29 ; CHECK-NEXT: [[INITVAL:%.*]] = load i32, i32* [[P]], align 4
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30 ; CHECK-NEXT: [[INITOP:%.*]] = load i32, i32* [[INCDEC_PTR]], align 4
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31 ; CHECK-NEXT: switch i32 [[INITOP]], label [[EXIT:%.*]] [
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32 ; CHECK-NEXT: i32 0, label [[BB0_CLONE:%.*]]
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33 ; CHECK-NEXT: i32 1, label [[BB1_CLONE:%.*]]
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34 ; CHECK-NEXT: ]
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35 ; CHECK: bb0:
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36 ; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
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37 ; CHECK: .split:
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38 ; CHECK-NEXT: [[MERGE:%.*]] = phi i32* [ [[PTR:%.*]], [[BB0:%.*]] ], [ [[INCDEC_PTR]], [[BB0_CLONE]] ]
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39 ; CHECK-NEXT: [[MERGE2:%.*]] = phi i32 [ 0, [[BB0]] ], [ [[INITVAL]], [[BB0_CLONE]] ]
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40 ; CHECK-NEXT: tail call void @use(i32 [[MERGE2]])
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41 ; CHECK-NEXT: br label [[INDIRECTGOTO:%.*]]
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42 ; CHECK: bb1:
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43 ; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
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44 ; CHECK: .split3:
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45 ; CHECK-NEXT: [[MERGE5:%.*]] = phi i32* [ [[PTR]], [[BB1:%.*]] ], [ [[INCDEC_PTR]], [[BB1_CLONE]] ]
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46 ; CHECK-NEXT: [[MERGE7:%.*]] = phi i32 [ 1, [[BB1]] ], [ [[INITVAL]], [[BB1_CLONE]] ]
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47 ; CHECK-NEXT: tail call void @use(i32 [[MERGE7]])
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48 ; CHECK-NEXT: br label [[INDIRECTGOTO]]
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49 ; CHECK: indirectgoto:
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50 ; CHECK-NEXT: [[P_ADDR_SINK:%.*]] = phi i32* [ [[MERGE5]], [[DOTSPLIT3]] ], [ [[MERGE]], [[DOTSPLIT]] ]
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51 ; CHECK-NEXT: [[PTR]] = getelementptr inbounds i32, i32* [[P_ADDR_SINK]], i64 1
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52 ; CHECK-NEXT: [[NEWP:%.*]] = load i32, i32* [[P_ADDR_SINK]], align 4
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53 ; CHECK-NEXT: [[IDX:%.*]] = sext i32 [[NEWP]] to i64
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54 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @simple.targets, i64 0, i64 [[IDX]]
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55 ; CHECK-NEXT: [[NEWOP:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8
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56 ; CHECK-NEXT: indirectbr i8* [[NEWOP]], [label [[BB0]], label %bb1]
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57 ; CHECK: exit:
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58 ; CHECK-NEXT: ret void
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59 ; CHECK: bb0.clone:
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60 ; CHECK-NEXT: br label [[DOTSPLIT]]
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61 ; CHECK: bb1.clone:
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62 ; CHECK-NEXT: br label [[DOTSPLIT3]]
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63 ;
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64 entry:
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65 %incdec.ptr = getelementptr inbounds i32, i32* %p, i64 1
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66 %initval = load i32, i32* %p, align 4
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67 %initop = load i32, i32* %incdec.ptr, align 4
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68 switch i32 %initop, label %exit [
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69 i32 0, label %bb0
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70 i32 1, label %bb1
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71 ]
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72
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73 bb0:
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74 %p.addr.0 = phi i32* [ %incdec.ptr, %entry ], [ %ptr, %indirectgoto ]
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75 %opcode.0 = phi i32 [ %initval, %entry ], [ 0, %indirectgoto ]
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76 tail call void @use(i32 %opcode.0)
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77 br label %indirectgoto
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78
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79 bb1:
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80 %p.addr.1 = phi i32* [ %incdec.ptr, %entry ], [ %ptr, %indirectgoto ]
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81 %opcode.1 = phi i32 [ %initval, %entry ], [ 1, %indirectgoto ]
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82 tail call void @use(i32 %opcode.1)
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83 br label %indirectgoto
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84
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85 indirectgoto:
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86 %p.addr.sink = phi i32* [ %p.addr.1, %bb1 ], [ %p.addr.0, %bb0 ]
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87 %ptr = getelementptr inbounds i32, i32* %p.addr.sink, i64 1
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88 %newp = load i32, i32* %p.addr.sink, align 4
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89 %idx = sext i32 %newp to i64
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90 %arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @simple.targets, i64 0, i64 %idx
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91 %newop = load i8*, i8** %arrayidx, align 8
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92 indirectbr i8* %newop, [label %bb0, label %bb1]
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93
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94 exit:
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95 ret void
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96 }
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97
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98 ; Don't try to break critical edges when several indirectbr point to a single block
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99 define void @multi(i32* nocapture readonly %p) {
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100 ; CHECK-LABEL: @multi(
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101 ; CHECK-NEXT: entry:
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102 ; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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103 ; CHECK-NEXT: [[INITVAL:%.*]] = load i32, i32* [[P]], align 4
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104 ; CHECK-NEXT: [[INITOP:%.*]] = load i32, i32* [[INCDEC_PTR]], align 4
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105 ; CHECK-NEXT: switch i32 [[INITOP]], label [[EXIT:%.*]] [
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106 ; CHECK-NEXT: i32 0, label [[BB0:%.*]]
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107 ; CHECK-NEXT: i32 1, label [[BB1:%.*]]
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108 ; CHECK-NEXT: ]
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109 ; CHECK: bb0:
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110 ; CHECK-NEXT: [[P_ADDR_0:%.*]] = phi i32* [ [[INCDEC_PTR]], [[ENTRY:%.*]] ], [ [[NEXT0:%.*]], [[BB0]] ], [ [[NEXT1:%.*]], [[BB1]] ]
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111 ; CHECK-NEXT: [[OPCODE_0:%.*]] = phi i32 [ [[INITVAL]], [[ENTRY]] ], [ 0, [[BB0]] ], [ 1, [[BB1]] ]
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112 ; CHECK-NEXT: tail call void @use(i32 [[OPCODE_0]])
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113 ; CHECK-NEXT: [[NEXT0]] = getelementptr inbounds i32, i32* [[P_ADDR_0]], i64 1
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114 ; CHECK-NEXT: [[NEWP0:%.*]] = load i32, i32* [[P_ADDR_0]], align 4
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115 ; CHECK-NEXT: [[IDX0:%.*]] = sext i32 [[NEWP0]] to i64
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116 ; CHECK-NEXT: [[ARRAYIDX0:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @multi.targets, i64 0, i64 [[IDX0]]
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117 ; CHECK-NEXT: [[NEWOP0:%.*]] = load i8*, i8** [[ARRAYIDX0]], align 8
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118 ; CHECK-NEXT: indirectbr i8* [[NEWOP0]], [label [[BB0]], label %bb1]
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119 ; CHECK: bb1:
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120 ; CHECK-NEXT: [[P_ADDR_1:%.*]] = phi i32* [ [[INCDEC_PTR]], [[ENTRY]] ], [ [[NEXT0]], [[BB0]] ], [ [[NEXT1]], [[BB1]] ]
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121 ; CHECK-NEXT: [[OPCODE_1:%.*]] = phi i32 [ [[INITVAL]], [[ENTRY]] ], [ 0, [[BB0]] ], [ 1, [[BB1]] ]
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122 ; CHECK-NEXT: tail call void @use(i32 [[OPCODE_1]])
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123 ; CHECK-NEXT: [[NEXT1]] = getelementptr inbounds i32, i32* [[P_ADDR_1]], i64 1
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124 ; CHECK-NEXT: [[NEWP1:%.*]] = load i32, i32* [[P_ADDR_1]], align 4
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125 ; CHECK-NEXT: [[IDX1:%.*]] = sext i32 [[NEWP1]] to i64
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126 ; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @multi.targets, i64 0, i64 [[IDX1]]
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127 ; CHECK-NEXT: [[NEWOP1:%.*]] = load i8*, i8** [[ARRAYIDX1]], align 8
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128 ; CHECK-NEXT: indirectbr i8* [[NEWOP1]], [label [[BB0]], label %bb1]
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129 ; CHECK: exit:
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130 ; CHECK-NEXT: ret void
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131 ;
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132 entry:
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133 %incdec.ptr = getelementptr inbounds i32, i32* %p, i64 1
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134 %initval = load i32, i32* %p, align 4
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135 %initop = load i32, i32* %incdec.ptr, align 4
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136 switch i32 %initop, label %exit [
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137 i32 0, label %bb0
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138 i32 1, label %bb1
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139 ]
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140
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141 bb0:
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142 %p.addr.0 = phi i32* [ %incdec.ptr, %entry ], [ %next0, %bb0 ], [ %next1, %bb1 ]
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143 %opcode.0 = phi i32 [ %initval, %entry ], [ 0, %bb0 ], [ 1, %bb1 ]
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144 tail call void @use(i32 %opcode.0)
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145 %next0 = getelementptr inbounds i32, i32* %p.addr.0, i64 1
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146 %newp0 = load i32, i32* %p.addr.0, align 4
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147 %idx0 = sext i32 %newp0 to i64
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148 %arrayidx0 = getelementptr inbounds [2 x i8*], [2 x i8*]* @multi.targets, i64 0, i64 %idx0
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149 %newop0 = load i8*, i8** %arrayidx0, align 8
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150 indirectbr i8* %newop0, [label %bb0, label %bb1]
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151
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152 bb1:
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153 %p.addr.1 = phi i32* [ %incdec.ptr, %entry ], [ %next0, %bb0 ], [ %next1, %bb1 ]
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154 %opcode.1 = phi i32 [ %initval, %entry ], [ 0, %bb0 ], [ 1, %bb1 ]
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155 tail call void @use(i32 %opcode.1)
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156 %next1 = getelementptr inbounds i32, i32* %p.addr.1, i64 1
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157 %newp1 = load i32, i32* %p.addr.1, align 4
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158 %idx1 = sext i32 %newp1 to i64
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159 %arrayidx1 = getelementptr inbounds [2 x i8*], [2 x i8*]* @multi.targets, i64 0, i64 %idx1
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160 %newop1 = load i8*, i8** %arrayidx1, align 8
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161 indirectbr i8* %newop1, [label %bb0, label %bb1]
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162
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163 exit:
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164 ret void
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165 }
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166
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167 ; Make sure we do the right thing for cases where the indirectbr branches to
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168 ; the block it terminates.
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169 define void @loop(i64* nocapture readonly %p) {
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170 ; CHECK-LABEL: @loop(
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171 ; CHECK-NEXT: entry:
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172 ; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
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173 ; CHECK: bb0:
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174 ; CHECK-NEXT: br label [[DOTSPLIT]]
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175 ; CHECK: .split:
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176 ; CHECK-NEXT: [[MERGE:%.*]] = phi i64 [ [[I_NEXT:%.*]], [[BB0:%.*]] ], [ 0, [[BB0_CLONE:%.*]] ]
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177 ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i64, i64* [[P:%.*]], i64 [[MERGE]]
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178 ; CHECK-NEXT: store i64 [[MERGE]], i64* [[TMP0]], align 4
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179 ; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[MERGE]], 1
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180 ; CHECK-NEXT: [[IDX:%.*]] = srem i64 [[MERGE]], 2
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181 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @loop.targets, i64 0, i64 [[IDX]]
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182 ; CHECK-NEXT: [[TARGET:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8
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183 ; CHECK-NEXT: indirectbr i8* [[TARGET]], [label [[BB0]], label %bb1]
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184 ; CHECK: bb1:
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185 ; CHECK-NEXT: ret void
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186 ;
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187 entry:
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188 br label %bb0
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189
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190 bb0:
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191 %i = phi i64 [ %i.next, %bb0 ], [ 0, %entry ]
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192 %tmp0 = getelementptr inbounds i64, i64* %p, i64 %i
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193 store i64 %i, i64* %tmp0, align 4
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194 %i.next = add nuw nsw i64 %i, 1
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195 %idx = srem i64 %i, 2
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196 %arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @loop.targets, i64 0, i64 %idx
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197 %target = load i8*, i8** %arrayidx, align 8
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198 indirectbr i8* %target, [label %bb0, label %bb1]
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199
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200 bb1:
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201 ret void
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202 }
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203
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204 ; Don't do anything for cases that contain no phis.
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205 define void @nophi(i32* %p) {
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206 ; CHECK-LABEL: @nophi(
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207 ; CHECK-NEXT: entry:
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208 ; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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209 ; CHECK-NEXT: [[INITOP:%.*]] = load i32, i32* [[INCDEC_PTR]], align 4
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210 ; CHECK-NEXT: switch i32 [[INITOP]], label [[EXIT:%.*]] [
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211 ; CHECK-NEXT: i32 0, label [[BB0:%.*]]
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212 ; CHECK-NEXT: i32 1, label [[BB1:%.*]]
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213 ; CHECK-NEXT: ]
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214 ; CHECK: bb0:
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215 ; CHECK-NEXT: tail call void @use(i32 0)
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216 ; CHECK-NEXT: br label [[INDIRECTGOTO:%.*]]
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217 ; CHECK: bb1:
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218 ; CHECK-NEXT: tail call void @use(i32 1)
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219 ; CHECK-NEXT: br label [[INDIRECTGOTO]]
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220 ; CHECK: indirectgoto:
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221 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P]] to i8*
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222 ; CHECK-NEXT: [[SUNKADDR:%.*]] = getelementptr inbounds i8, i8* [[TMP0]], i64 4
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223 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[SUNKADDR]] to i32*
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parents:
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224 ; CHECK-NEXT: [[NEWP:%.*]] = load i32, i32* [[TMP1]], align 4
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parents:
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225 ; CHECK-NEXT: [[IDX:%.*]] = sext i32 [[NEWP]] to i64
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parents:
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226 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @nophi.targets, i64 0, i64 [[IDX]]
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parents:
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227 ; CHECK-NEXT: [[NEWOP:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8
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parents:
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228 ; CHECK-NEXT: indirectbr i8* [[NEWOP]], [label [[BB0]], label %bb1]
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parents:
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229 ; CHECK: exit:
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parents:
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230 ; CHECK-NEXT: ret void
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parents:
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231 ;
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parents:
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232 entry:
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parents:
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233 %incdec.ptr = getelementptr inbounds i32, i32* %p, i64 1
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parents:
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234 %initop = load i32, i32* %incdec.ptr, align 4
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parents:
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235 switch i32 %initop, label %exit [
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236 i32 0, label %bb0
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parents:
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237 i32 1, label %bb1
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parents:
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238 ]
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parents:
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239
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parents:
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240 bb0:
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parents:
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241 tail call void @use(i32 0) br label %indirectgoto
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parents:
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242
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parents:
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243 bb1:
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parents:
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244 tail call void @use(i32 1)
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parents:
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245 br label %indirectgoto
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parents:
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246
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247 indirectgoto:
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248 %newp = load i32, i32* %incdec.ptr, align 4
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249 %idx = sext i32 %newp to i64
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parents:
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250 %arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @nophi.targets, i64 0, i64 %idx
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parents:
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251 %newop = load i8*, i8** %arrayidx, align 8
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parents:
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252 indirectbr i8* %newop, [label %bb0, label %bb1]
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253
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254 exit:
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255 ret void
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parents:
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256 }
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parents:
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257
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parents:
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258 ; Don't do anything if the edge isn't critical.
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259 define i32 @noncritical(i32 %k, i8* %p)
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parents:
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260 ; CHECK-LABEL: @noncritical(
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parents:
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261 ; CHECK-NEXT: entry:
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parents:
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262 ; CHECK-NEXT: [[D:%.*]] = add i32 [[K:%.*]], 1
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parents:
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263 ; CHECK-NEXT: indirectbr i8* [[P:%.*]], [label [[BB0:%.*]], label %bb1]
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parents:
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264 ; CHECK: bb0:
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parents:
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265 ; CHECK-NEXT: [[R0:%.*]] = sub i32 [[K]], [[D]]
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parents:
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266 ; CHECK-NEXT: br label [[EXIT:%.*]]
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parents:
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267 ; CHECK: bb1:
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parents:
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268 ; CHECK-NEXT: [[R1:%.*]] = sub i32 [[D]], [[K]]
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parents:
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269 ; CHECK-NEXT: br label [[EXIT]]
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parents:
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270 ; CHECK: exit:
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parents:
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271 ; CHECK-NEXT: [[V:%.*]] = phi i32 [ [[R0]], [[BB0]] ], [ [[R1]], [[BB1:%.*]] ]
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parents:
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272 ; CHECK-NEXT: ret i32 0
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parents:
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273 ;
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parents:
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274 {
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275 entry:
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parents:
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276 %d = add i32 %k, 1
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parents:
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277 indirectbr i8* %p, [label %bb0, label %bb1]
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parents:
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278
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279 bb0:
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280 %v00 = phi i32 [%k, %entry]
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parents:
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281 %v01 = phi i32 [%d, %entry]
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parents:
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282 %r0 = sub i32 %v00, %v01
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parents:
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283 br label %exit
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parents:
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284
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285 bb1:
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parents:
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286 %v10 = phi i32 [%d, %entry]
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parents:
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287 %v11 = phi i32 [%k, %entry]
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parents:
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288 %r1 = sub i32 %v10, %v11
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parents:
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289 br label %exit
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290
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291 exit:
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292 %v = phi i32 [%r0, %bb0], [%r1, %bb1]
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293 ret i32 0
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parents:
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294 }