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1 //===-- LanaiISelDAGToDAG.cpp - A dag to dag inst selector for Lanai ------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines an instruction selector for the Lanai target.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "Lanai.h"
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15 #include "LanaiMachineFunctionInfo.h"
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16 #include "LanaiRegisterInfo.h"
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17 #include "LanaiSubtarget.h"
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18 #include "LanaiTargetMachine.h"
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19 #include "llvm/CodeGen/MachineConstantPool.h"
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20 #include "llvm/CodeGen/MachineFrameInfo.h"
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21 #include "llvm/CodeGen/MachineFunction.h"
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22 #include "llvm/CodeGen/MachineInstrBuilder.h"
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23 #include "llvm/CodeGen/MachineRegisterInfo.h"
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24 #include "llvm/CodeGen/SelectionDAGISel.h"
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25 #include "llvm/IR/CFG.h"
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26 #include "llvm/IR/GlobalValue.h"
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27 #include "llvm/IR/Instructions.h"
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28 #include "llvm/IR/Intrinsics.h"
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29 #include "llvm/IR/Type.h"
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30 #include "llvm/Support/Debug.h"
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31 #include "llvm/Support/ErrorHandling.h"
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32 #include "llvm/Support/raw_ostream.h"
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33 #include "llvm/Target/TargetMachine.h"
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34
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35 using namespace llvm;
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36
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37 #define DEBUG_TYPE "lanai-isel"
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38
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39 //===----------------------------------------------------------------------===//
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40 // Instruction Selector Implementation
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41 //===----------------------------------------------------------------------===//
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42
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43 //===----------------------------------------------------------------------===//
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44 // LanaiDAGToDAGISel - Lanai specific code to select Lanai machine
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45 // instructions for SelectionDAG operations.
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46 //===----------------------------------------------------------------------===//
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47 namespace {
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48
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49 class LanaiDAGToDAGISel : public SelectionDAGISel {
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50 public:
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51 explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine)
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52 : SelectionDAGISel(TargetMachine) {}
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53
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54 bool runOnMachineFunction(MachineFunction &MF) override {
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55 return SelectionDAGISel::runOnMachineFunction(MF);
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56 }
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57
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58 // Pass Name
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59 StringRef getPassName() const override {
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60 return "Lanai DAG->DAG Pattern Instruction Selection";
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61 }
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62
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63 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
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64 std::vector<SDValue> &OutOps) override;
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65
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66 private:
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67 // Include the pieces autogenerated from the target description.
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68 #include "LanaiGenDAGISel.inc"
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69
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70 // Instruction Selection not handled by the auto-generated tablgen
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71 void Select(SDNode *N) override;
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72
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73 // Support functions for the opcodes of Instruction Selection
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74 // not handled by the auto-generated tablgen
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75 void selectFrameIndex(SDNode *N);
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76
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77 // Complex Pattern for address selection.
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78 bool selectAddrRi(SDValue Addr, SDValue &Base, SDValue &Offset,
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79 SDValue &AluOp);
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80 bool selectAddrRr(SDValue Addr, SDValue &R1, SDValue &R2, SDValue &AluOp);
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81 bool selectAddrSls(SDValue Addr, SDValue &Offset);
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82 bool selectAddrSpls(SDValue Addr, SDValue &Base, SDValue &Offset,
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83 SDValue &AluOp);
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84
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85 // getI32Imm - Return a target constant with the specified value, of type i32.
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86 inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
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87 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
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88 }
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89
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90 private:
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91 bool selectAddrRiSpls(SDValue Addr, SDValue &Base, SDValue &Offset,
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92 SDValue &AluOp, bool RiMode);
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93 };
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94
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95 bool canBeRepresentedAsSls(const ConstantSDNode &CN) {
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96 // Fits in 21-bit signed immediate and two low-order bits are zero.
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97 return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0);
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98 }
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99
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100 } // namespace
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101
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102 // Helper functions for ComplexPattern used on LanaiInstrInfo
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103 // Used on Lanai Load/Store instructions.
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104 bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) {
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105 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
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106 SDLoc DL(Addr);
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107 // Loading from a constant address.
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108 if (canBeRepresentedAsSls(*CN)) {
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109 int32_t Imm = CN->getSExtValue();
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110 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
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111 return true;
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112 }
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113 }
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114 if (Addr.getOpcode() == ISD::OR &&
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115 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) {
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116 Offset = Addr.getOperand(1).getOperand(0);
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117 return true;
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118 }
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119 return false;
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120 }
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121
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122 bool LanaiDAGToDAGISel::selectAddrRiSpls(SDValue Addr, SDValue &Base,
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123 SDValue &Offset, SDValue &AluOp,
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124 bool RiMode) {
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125 SDLoc DL(Addr);
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126
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127 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
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128 if (RiMode) {
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129 // Fits in 16-bit signed immediate.
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130 if (isInt<16>(CN->getSExtValue())) {
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131 int16_t Imm = CN->getSExtValue();
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132 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
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133 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
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134 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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135 return true;
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136 }
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137 // Allow SLS to match if the constant doesn't fit in 16 bits but can be
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138 // represented as an SLS.
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139 if (canBeRepresentedAsSls(*CN))
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140 return false;
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141 } else {
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142 // Fits in 10-bit signed immediate.
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143 if (isInt<10>(CN->getSExtValue())) {
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144 int16_t Imm = CN->getSExtValue();
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145 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
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146 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
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147 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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148 return true;
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149 }
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150 }
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151 }
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152
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153 // if Address is FI, get the TargetFrameIndex.
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154 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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155 Base = CurDAG->getTargetFrameIndex(
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156 FIN->getIndex(),
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157 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
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158 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
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159 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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160 return true;
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161 }
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162
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163 // Skip direct calls
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164 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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165 Addr.getOpcode() == ISD::TargetGlobalAddress))
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166 return false;
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167
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168 // Address of the form imm + reg
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169 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode());
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170 if (AluOperator == ISD::ADD) {
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171 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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172 // Addresses of the form FI+const
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173 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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174 if ((RiMode && isInt<16>(CN->getSExtValue())) ||
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175 (!RiMode && isInt<10>(CN->getSExtValue()))) {
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176 // If the first operand is a FI, get the TargetFI Node
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177 if (FrameIndexSDNode *FIN =
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178 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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179 Base = CurDAG->getTargetFrameIndex(
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180 FIN->getIndex(),
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181 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
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182 } else {
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183 Base = Addr.getOperand(0);
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184 }
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185
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186 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i32);
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187 return true;
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188 }
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189 }
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190
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191 // Let SLS match SMALL instead of RI.
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192 if (AluOperator == ISD::OR && RiMode &&
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193 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL)
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194 return false;
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195
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196 Base = Addr;
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197 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
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198 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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199 return true;
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200 }
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201
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202 bool LanaiDAGToDAGISel::selectAddrRi(SDValue Addr, SDValue &Base,
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203 SDValue &Offset, SDValue &AluOp) {
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204 return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RiMode=*/true);
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205 }
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206
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207 bool LanaiDAGToDAGISel::selectAddrSpls(SDValue Addr, SDValue &Base,
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208 SDValue &Offset, SDValue &AluOp) {
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209 return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RiMode=*/false);
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210 }
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211
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212 bool LanaiDAGToDAGISel::selectAddrRr(SDValue Addr, SDValue &R1, SDValue &R2,
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213 SDValue &AluOp) {
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214 // if Address is FI, get the TargetFrameIndex.
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215 if (Addr.getOpcode() == ISD::FrameIndex)
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216 return false;
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217
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218 // Skip direct calls
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219 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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220 Addr.getOpcode() == ISD::TargetGlobalAddress))
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221 return false;
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222
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223 // Address of the form OP + OP
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224 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode());
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225 LPAC::AluCode AluCode = LPAC::isdToLanaiAluCode(AluOperator);
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226 if (AluCode != LPAC::UNKNOWN) {
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227 // Skip addresses of the form FI OP const
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228 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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229 if (isInt<16>(CN->getSExtValue()))
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230 return false;
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231
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232 // Skip addresses with hi/lo operands
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233 if (Addr.getOperand(0).getOpcode() == LanaiISD::HI ||
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234 Addr.getOperand(0).getOpcode() == LanaiISD::LO ||
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235 Addr.getOperand(0).getOpcode() == LanaiISD::SMALL ||
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236 Addr.getOperand(1).getOpcode() == LanaiISD::HI ||
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237 Addr.getOperand(1).getOpcode() == LanaiISD::LO ||
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238 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL)
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239 return false;
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240
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241 // Addresses of the form register OP register
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242 R1 = Addr.getOperand(0);
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243 R2 = Addr.getOperand(1);
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244 AluOp = CurDAG->getTargetConstant(AluCode, SDLoc(Addr), MVT::i32);
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245 return true;
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246 }
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247
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248 // Skip addresses with zero offset
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249 return false;
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250 }
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251
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252 bool LanaiDAGToDAGISel::SelectInlineAsmMemoryOperand(
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253 const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
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254 SDValue Op0, Op1, AluOp;
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255 switch (ConstraintCode) {
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256 default:
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257 return true;
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258 case InlineAsm::Constraint_m: // memory
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259 if (!selectAddrRr(Op, Op0, Op1, AluOp) &&
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260 !selectAddrRi(Op, Op0, Op1, AluOp))
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261 return true;
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262 break;
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263 }
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264
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265 OutOps.push_back(Op0);
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266 OutOps.push_back(Op1);
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267 OutOps.push_back(AluOp);
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268 return false;
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269 }
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270
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271 // Select instructions not customized! Used for
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272 // expanded, promoted and normal instructions
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273 void LanaiDAGToDAGISel::Select(SDNode *Node) {
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274 unsigned Opcode = Node->getOpcode();
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275
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276 // Dump information about the Node being selected
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277 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
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278
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279 // If we have a custom node, we already have selected!
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280 if (Node->isMachineOpcode()) {
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281 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
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282 return;
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283 }
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284
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285 // Instruction Selection not handled by the auto-generated
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286 // tablegen selection should be handled here.
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287 switch (Opcode) {
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288 case ISD::FrameIndex:
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289 selectFrameIndex(Node);
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290 return;
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291 default:
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292 break;
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293 }
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294
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295 // Select the default instruction
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296 SelectCode(Node);
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297 }
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298
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299 void LanaiDAGToDAGISel::selectFrameIndex(SDNode *Node) {
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300 SDLoc DL(Node);
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301 SDValue Imm = CurDAG->getTargetConstant(0, DL, MVT::i32);
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302 int FI = dyn_cast<FrameIndexSDNode>(Node)->getIndex();
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303 EVT VT = Node->getValueType(0);
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304 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
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305 unsigned Opc = Lanai::ADD_I_LO;
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306 if (Node->hasOneUse()) {
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307 CurDAG->SelectNodeTo(Node, Opc, VT, TFI, Imm);
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308 return;
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309 }
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310 ReplaceNode(Node, CurDAG->getMachineNode(Opc, DL, VT, TFI, Imm));
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311 }
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312
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313 // createLanaiISelDag - This pass converts a legalized DAG into a
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314 // Lanai-specific DAG, ready for instruction scheduling.
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315 FunctionPass *llvm::createLanaiISelDag(LanaiTargetMachine &TM) {
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316 return new LanaiDAGToDAGISel(TM);
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317 }
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