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annotate lib/Target/SystemZ/SystemZScheduleZ196.td @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents
children 803732b1fca8
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120
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1 //=- SystemZScheduleZ196.td - SystemZ Scheduling Definitions ---*- tblgen -*-=//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the machine model for Z196 to support instruction
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11 // scheduling and other instruction cost heuristics.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 def Z196Model : SchedMachineModel {
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16
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17 let UnsupportedFeatures = Arch9UnsupportedFeatures.List;
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18
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19 let IssueWidth = 5;
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20 let MicroOpBufferSize = 40; // Issue queues
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21 let LoadLatency = 1; // Optimistic load latency.
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22
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23 let PostRAScheduler = 1;
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24
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25 // Extra cycles for a mispredicted branch.
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26 let MispredictPenalty = 8;
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27 }
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28
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29 let SchedModel = Z196Model in {
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30
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31 // These definitions could be put in a subtarget common include file,
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32 // but it seems the include system in Tablegen currently rejects
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33 // multiple includes of same file.
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34 def : WriteRes<GroupAlone, []> {
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35 let NumMicroOps = 0;
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36 let BeginGroup = 1;
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37 let EndGroup = 1;
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38 }
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39 def : WriteRes<EndGroup, []> {
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40 let NumMicroOps = 0;
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41 let EndGroup = 1;
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42 }
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43 def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
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44 def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
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45 def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
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46 def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
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47 def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
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48 def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
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49 def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
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50 def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
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51 def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
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52 def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
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53 def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
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54 def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
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55 def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
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56 def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
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57
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58 // Execution units.
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59 def Z196_FXUnit : ProcResource<2>;
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60 def Z196_LSUnit : ProcResource<2>;
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61 def Z196_FPUnit : ProcResource<1>;
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62
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63 // Subtarget specific definitions of scheduling resources.
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64 def : WriteRes<FXU, [Z196_FXUnit]> { let Latency = 1; }
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65 def : WriteRes<LSU, [Z196_LSUnit]> { let Latency = 4; }
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66 def : WriteRes<LSU_lat1, [Z196_LSUnit]> { let Latency = 1; }
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67 def : WriteRes<FPU, [Z196_FPUnit]> { let Latency = 8; }
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68 def : WriteRes<FPU2, [Z196_FPUnit, Z196_FPUnit]> { let Latency = 9; }
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69
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70 // -------------------------- INSTRUCTIONS ---------------------------------- //
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71
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72 // InstRW constructs have been used in order to preserve the
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73 // readability of the InstrInfo files.
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74
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75 // For each instruction, as matched by a regexp, provide a list of
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76 // resources that it needs. These will be combined into a SchedClass.
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77
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78 //===----------------------------------------------------------------------===//
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79 // Stack allocation
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80 //===----------------------------------------------------------------------===//
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81
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82 def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
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83
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84 //===----------------------------------------------------------------------===//
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85 // Branch instructions
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86 //===----------------------------------------------------------------------===//
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87
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88 // Branch
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89 def : InstRW<[LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
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90 def : InstRW<[LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
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91 def : InstRW<[LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
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92 def : InstRW<[LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
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93 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BRCT(G)?$")>;
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94 def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone], (instregex "BRX(H|LE)$")>;
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95
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96 // Compare and branch
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97 def : InstRW<[FXU, LSU, Lat5, GroupAlone],
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98 (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
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99 def : InstRW<[FXU, LSU, Lat5, GroupAlone],
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100 (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
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101
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102 //===----------------------------------------------------------------------===//
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103 // Trap instructions
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104 //===----------------------------------------------------------------------===//
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105
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106 // Trap
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107 def : InstRW<[LSU, EndGroup], (instregex "(Cond)?Trap$")>;
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108
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109 // Compare and trap
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110 def : InstRW<[FXU], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
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111 def : InstRW<[FXU], (instregex "CL(G)?RT(Asm.*)?$")>;
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112 def : InstRW<[FXU], (instregex "CL(F|G)IT(Asm.*)?$")>;
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113
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114 //===----------------------------------------------------------------------===//
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115 // Call and return instructions
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116 //===----------------------------------------------------------------------===//
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117
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118 // Call
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119 def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRAS$")>;
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120 def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
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121 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
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122 def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
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123
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124 // Return
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125 def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
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126 def : InstRW<[LSU_lat1, EndGroup], (instregex "CondReturn$")>;
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127
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128 //===----------------------------------------------------------------------===//
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129 // Select instructions
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130 //===----------------------------------------------------------------------===//
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131
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132 // Select pseudo
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133 def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
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134
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135 // CondStore pseudos
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136 def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
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137 def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
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138 def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
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139 def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
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140 def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
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141 def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
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142
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143 //===----------------------------------------------------------------------===//
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144 // Move instructions
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145 //===----------------------------------------------------------------------===//
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146
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147 // Moves
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148 def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
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149 def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
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150
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151 // Move character
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152 def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
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153
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154 // Pseudo -> reg move
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155 def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
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156 def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
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157 def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
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158 def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
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159 def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
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160
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161 // Loads
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162 def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
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163 def : InstRW<[LSU], (instregex "LG(RL)?$")>;
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164 def : InstRW<[LSU], (instregex "L128$")>;
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165
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166 def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
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167 def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
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168
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169 def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
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170 def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
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171 def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
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172
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173 // Load and test
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174 def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
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175 def : InstRW<[FXU], (instregex "LT(G)?R$")>;
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176
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177 // Stores
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178 def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
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179 def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
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180 def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
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181
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182 // String moves.
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183 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
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184
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185 //===----------------------------------------------------------------------===//
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186 // Conditional move instructions
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187 //===----------------------------------------------------------------------===//
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188
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189 def : InstRW<[FXU, Lat2, EndGroup], (instregex "LOC(G)?R(Asm.*)?$")>;
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190 def : InstRW<[FXU, Lat2, EndGroup], (instregex "LOC(G)?HI(Asm.*)?$")>;
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191 def : InstRW<[FXU, LSU, Lat6, EndGroup], (instregex "LOC(G)?(Asm.*)?$")>;
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192 def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "STOC(G)?(Asm.*)?$")>;
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193
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194 //===----------------------------------------------------------------------===//
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195 // Sign extensions
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196 //===----------------------------------------------------------------------===//
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197 def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
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198 def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
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199
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200 def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
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201 def : InstRW<[FXU], (instregex "LTGFR$")>;
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202
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203 def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
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204 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
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205 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
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206 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
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207 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
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208
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209 //===----------------------------------------------------------------------===//
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210 // Zero extensions
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211 //===----------------------------------------------------------------------===//
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212
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213 def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
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214 def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
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215 def : InstRW<[FXU], (instregex "LLG(C|F|H|T)R$")>;
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216 def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
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217 def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
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218 def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
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219 def : InstRW<[LSU], (instregex "LLHRL$")>;
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220 def : InstRW<[LSU], (instregex "LLG(C|F|H|T|FRL|HRL)$")>;
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221
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222 //===----------------------------------------------------------------------===//
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223 // Truncations
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224 //===----------------------------------------------------------------------===//
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225
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226 def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
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227 def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
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228
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229 //===----------------------------------------------------------------------===//
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230 // Multi-register moves
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231 //===----------------------------------------------------------------------===//
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232
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233 // Load multiple (estimated average of 5 ops)
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234 def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
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235 (instregex "LM(H|Y|G)?$")>;
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236
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237 // Store multiple (estimated average of 3 ops)
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238 def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
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239 (instregex "STM(H|Y|G)?$")>;
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240
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241 //===----------------------------------------------------------------------===//
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242 // Byte swaps
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243 //===----------------------------------------------------------------------===//
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244
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245 def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
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246 def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
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247 def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
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248
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249 //===----------------------------------------------------------------------===//
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250 // Load address instructions
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251 //===----------------------------------------------------------------------===//
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252
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253 def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
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254
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255 // Load the Global Offset Table address
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256 def : InstRW<[FXU], (instregex "GOT$")>;
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257
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258 //===----------------------------------------------------------------------===//
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259 // Absolute and Negation
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260 //===----------------------------------------------------------------------===//
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261
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262 def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
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263 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
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264 def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
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265 def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
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266 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
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267
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268 //===----------------------------------------------------------------------===//
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269 // Insertion
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270 //===----------------------------------------------------------------------===//
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271
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272 def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
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273 def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
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274 def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
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275 def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
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276 def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
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277 def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
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278 def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
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279 def : InstRW<[FXU], (instregex "IILF(64)?$")>;
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280 def : InstRW<[FXU], (instregex "IILH(64)?$")>;
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281 def : InstRW<[FXU], (instregex "IILL(64)?$")>;
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282
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283 //===----------------------------------------------------------------------===//
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284 // Addition
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285 //===----------------------------------------------------------------------===//
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286
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287 def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
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288 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AH(Y)?$")>;
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289 def : InstRW<[FXU], (instregex "AIH$")>;
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290 def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
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291 def : InstRW<[FXU], (instregex "AGFI$")>;
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292 def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
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293 def : InstRW<[FXU], (instregex "AGR(K)?$")>;
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294 def : InstRW<[FXU], (instregex "AHI(K)?$")>;
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295 def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
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296 def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
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297 def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
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298 def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
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299 def : InstRW<[FXU], (instregex "ALGHSIK$")>;
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300 def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
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301 def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
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302 def : InstRW<[FXU], (instregex "ALR(K)?$")>;
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303 def : InstRW<[FXU], (instregex "AR(K)?$")>;
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304 def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
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305
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306 // Logical addition with carry
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307 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
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308 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
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309
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310 // Add with sign extension (32 -> 64)
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311 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AGF$")>;
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312 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "AGFR$")>;
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313
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314 //===----------------------------------------------------------------------===//
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315 // Subtraction
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316 //===----------------------------------------------------------------------===//
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317
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318 def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
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319 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SH(Y)?$")>;
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320 def : InstRW<[FXU], (instregex "SGR(K)?$")>;
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321 def : InstRW<[FXU], (instregex "SLFI$")>;
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322 def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
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323 def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
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324 def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
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325 def : InstRW<[FXU], (instregex "SLR(K)?$")>;
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326 def : InstRW<[FXU], (instregex "SR(K)?$")>;
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327
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328 // Subtraction with borrow
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329 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
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330 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
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331
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332 // Subtraction with sign extension (32 -> 64)
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333 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SGF$")>;
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334 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "SGFR$")>;
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335
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336 //===----------------------------------------------------------------------===//
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337 // AND
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diff changeset
338 //===----------------------------------------------------------------------===//
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339
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340 def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
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parents:
diff changeset
341 def : InstRW<[FXU], (instregex "NGR(K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
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342 def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
343 def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
344 def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
345 def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
346 def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
347 def : InstRW<[FXU], (instregex "NILF(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
348 def : InstRW<[FXU], (instregex "NILH(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
349 def : InstRW<[FXU], (instregex "NILL(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
350 def : InstRW<[FXU], (instregex "NR(K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
351 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
352
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parents:
diff changeset
353 //===----------------------------------------------------------------------===//
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parents:
diff changeset
354 // OR
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parents:
diff changeset
355 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
356
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parents:
diff changeset
357 def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
358 def : InstRW<[FXU], (instregex "OGR(K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
359 def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
360 def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
361 def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
362 def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
363 def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
364 def : InstRW<[FXU], (instregex "OILF(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
365 def : InstRW<[FXU], (instregex "OILH(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
366 def : InstRW<[FXU], (instregex "OILL(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
367 def : InstRW<[FXU], (instregex "OR(K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
368 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
369
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parents:
diff changeset
370 //===----------------------------------------------------------------------===//
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parents:
diff changeset
371 // XOR
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
372 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
373
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parents:
diff changeset
374 def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
375 def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
376 def : InstRW<[FXU], (instregex "XIFMux$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
377 def : InstRW<[FXU], (instregex "XGR(K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
378 def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
379 def : InstRW<[FXU], (instregex "XILF(64)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
380 def : InstRW<[FXU], (instregex "XR(K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
381 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
382
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parents:
diff changeset
383 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
384 // Multiplication
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
385 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
386
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
387 def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
388 def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
389 def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
390 def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
391 def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
392 def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
393 def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
394 def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
395 def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
396 def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
397
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parents:
diff changeset
398 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
399 // Division and remainder
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
400 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
401
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
402 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
403 (instregex "DSG(F)?R$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
404 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
405 (instregex "DSG(F)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
406 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
407 (instregex "DL(G)?R$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
408 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
409 (instregex "DL(G)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
410
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
411 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
412 // Shifts
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
413 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
414
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
415 def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
416 def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
417 def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
418 def : InstRW<[FXU, Lat2], (instregex "SLA(K)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
419
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
420 // Rotate
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
421 def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
422
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
423 // Rotate and insert
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
424 def : InstRW<[FXU], (instregex "RISBG(32)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
425 def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
426 def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
427 def : InstRW<[FXU], (instregex "RISBMux$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
428
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
429 // Rotate and Select
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
430 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
431
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
432 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
433 // Comparison
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
434 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
435
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
436 def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
437 def : InstRW<[FXU], (instregex "CFI(Mux)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
438 def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
439 def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
440 def : InstRW<[FXU], (instregex "C(G)?R$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
441 def : InstRW<[FXU], (instregex "C(HI|IH)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
442 def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
443 def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
444 def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
445 def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
446 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
447 def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
448 def : InstRW<[FXU], (instregex "CLGR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
449 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
450 def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
451 def : InstRW<[FXU], (instregex "CLIH$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
452 def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
453 def : InstRW<[FXU], (instregex "CLR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
454 def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
455
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
456 // Compare halfword
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
457 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CH(Y|RL)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
458 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CGH(RL)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
459 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CHHSI$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
460
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
461 // Compare with sign extension (32 -> 64)
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
462 def : InstRW<[FXU, FXU, LSU, Lat6, Lat2, GroupAlone], (instregex "CGF(RL)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
463 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "CGFR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
464
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
465 // Compare logical character
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
466 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "CLC$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
467
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
468 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
469
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
470 // Test under mask
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
471 def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
472 def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
473 def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
474 def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
475 def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
476 def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
477
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
478 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
479 // Prefetch
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
480 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
481
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
482 def : InstRW<[LSU, GroupAlone], (instregex "PFD(RL)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
483
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
484 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
485 // Atomic operations
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
486 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
487
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
488 def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
489
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
490 def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
491 def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
492 def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
493 def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
494 def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
495
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
496 // Compare and swap
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
497 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
498
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
499 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
500 // Access registers
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
501 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
502
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
503 // Extract/set/copy access register
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
504 def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
505
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mir3636
parents:
diff changeset
506 // Load address extended
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
507 def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
508
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
509 // Load/store access multiple (not modeled precisely)
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
510 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
511
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
512 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
513 // Program mask and addressing mode
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
514 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
515
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
516 // Insert Program Mask
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
517 def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
518
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
519 // Set Program Mask
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
520 def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
521
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
522 // Branch and link
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
523 def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
524
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
525 // Test addressing mode
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
526 def : InstRW<[FXU], (instregex "TAM$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
527
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
528 // Set addressing mode
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
529 def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
530
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
531 // Branch (and save) and set mode.
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
532 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
533 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
534
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
535 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
536 // Miscellaneous Instructions.
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
537 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
538
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
539 // Find leftmost one
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
540 def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
541
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
542 // Population count
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
543 def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
544
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
545 // Extend
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
546 def : InstRW<[FXU], (instregex "AEXT128_64$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
547 def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
548
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
549 // String instructions
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
550 def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
551
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
552 // Move with key
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
553 def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
554
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
555 // Extract CPU Time
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
556 def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
557
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
558 // Execute
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
559 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
560
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
561 // Program return
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
562 def : InstRW<[FXU, Lat30], (instregex "PR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
563
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
564 // Inline assembly
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
565 def : InstRW<[FXU, LSU, Lat15], (instregex "STCK$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
566 def : InstRW<[FXU, LSU, Lat12], (instregex "STCKF$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
567 def : InstRW<[LSU, FXU, Lat5], (instregex "STCKE$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
568 def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
569 def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
570
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
571 // Store real address
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
572 def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
573
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
574 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
575 // .insn directive instructions
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
576 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
577
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
578 // An "empty" sched-class will be assigned instead of the "invalid sched-class".
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
579 // getNumDecoderSlots() will then return 1 instead of 0.
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
580 def : InstRW<[], (instregex "Insn.*")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
581
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
582
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
583 // ----------------------------- Floating point ----------------------------- //
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
584
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
585 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
586 // FP: Select instructions
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
587 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
588
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
589 def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
590 def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
591 def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
592
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
593 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
594 // FP: Move instructions
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
595 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
596
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
597 // Load zero
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
598 def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
599 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
600
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
601 // Load
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
602 def : InstRW<[FXU], (instregex "LER$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
603 def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
604 def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
605 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
606
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
607 // Load and Test
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
608 def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
609 def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
610 def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
611 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
612 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
613 (instregex "LTXBRCompare(_VecPseudo)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
614
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
615 // Copy sign
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
616 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
617 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
618
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
619 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
620 // FP: Load instructions
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
621 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
622
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
623 def : InstRW<[LSU], (instregex "LE(Y)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
624 def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
625 def : InstRW<[LSU], (instregex "LX$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
626
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
627 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
628 // FP: Store instructions
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
629 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
630
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
631 def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
632 def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
633 def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
634
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
635 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
636 // FP: Conversion instructions
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
637 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
638
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
639 // Load rounded
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
640 def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
641 def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
642 def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
643
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
644 // Load lengthened
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
645 def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
646 def : InstRW<[FPU], (instregex "LDEBR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
647 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
648 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
649
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
650 // Convert from fixed / logical
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
651 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
652 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
653 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
654 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
655 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
656 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
657
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
658 // Convert to fixed / logical
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
659 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
660 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
661 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
662 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
663 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
664 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
665
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
666 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
667 // FP: Unary arithmetic
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
668 //===----------------------------------------------------------------------===//
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
669
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
670 // Load Complement / Negative / Positive
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
671 def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
672 def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
673 def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
674 def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
675 def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
676 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
677
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678 // Square root
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679 def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
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680 def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
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681 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
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682
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683 // Load FP integer
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684 def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
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685 def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
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686 def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
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687
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688 //===----------------------------------------------------------------------===//
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689 // FP: Binary arithmetic
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690 //===----------------------------------------------------------------------===//
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691
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692 // Addition
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693 def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
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694 def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
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695 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
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696
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697 // Subtraction
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698 def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
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699 def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
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700 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
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701
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702 // Multiply
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703 def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
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704 def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
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705 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
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706 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
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707 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
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708
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709 // Multiply and add / subtract
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710 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
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711 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
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712 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
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713 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
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714
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715 // Division
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716 def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
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717 def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
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718 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
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719
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720 //===----------------------------------------------------------------------===//
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721 // FP: Comparisons
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722 //===----------------------------------------------------------------------===//
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723
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724 // Compare
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725 def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
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726 def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
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727 def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
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728
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729 // Test Data Class
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730 def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
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731 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
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732
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733 }
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734