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annotate test/CodeGen/AArch64/arm64-umaxv.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 3a76565eade5
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
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1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
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2
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3 define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp {
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4 ; CHECK-LABEL: vmax_u8x8:
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5 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
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6 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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7 ; CHECK-NOT: and
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8 ; CHECK: cbz [[REG2]],
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9 entry:
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10 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind
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11 %tmp = trunc i32 %vmaxv.i to i8
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12 %tobool = icmp eq i8 %tmp, 0
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13 br i1 %tobool, label %return, label %if.then
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14
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15 if.then:
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16 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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17 br label %return
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18
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19 return:
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20 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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21 ret i32 %retval.0
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22 }
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23
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24 declare i32 @bar(...)
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25
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26 define i32 @vmax_u4x16(<4 x i16> %a) nounwind ssp {
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27 ; CHECK-LABEL: vmax_u4x16:
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28 ; CHECK: umaxv.4h h[[REG:[0-9]+]], v0
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29 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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30 ; CHECK-NOT: and
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31 ; CHECK: cbz [[REG2]],
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32 entry:
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33 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind
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34 %tmp = trunc i32 %vmaxv.i to i16
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35 %tobool = icmp eq i16 %tmp, 0
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36 br i1 %tobool, label %return, label %if.then
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37
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38 if.then:
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39 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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40 br label %return
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41
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42 return:
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43 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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44 ret i32 %retval.0
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45 }
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46
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47 define i32 @vmax_u8x16(<8 x i16> %a) nounwind ssp {
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48 ; CHECK-LABEL: vmax_u8x16:
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49 ; CHECK: umaxv.8h h[[REG:[0-9]+]], v0
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50 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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51 ; CHECK-NOT: and
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52 ; CHECK: cbz [[REG2]],
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53 entry:
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54 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind
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55 %tmp = trunc i32 %vmaxv.i to i16
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56 %tobool = icmp eq i16 %tmp, 0
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57 br i1 %tobool, label %return, label %if.then
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58
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59 if.then:
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60 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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61 br label %return
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62
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63 return:
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64 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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65 ret i32 %retval.0
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66 }
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67
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68 define i32 @vmax_u16x8(<16 x i8> %a) nounwind ssp {
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69 ; CHECK-LABEL: vmax_u16x8:
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70 ; CHECK: umaxv.16b b[[REG:[0-9]+]], v0
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parents:
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71 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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72 ; CHECK-NOT: and
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73 ; CHECK: cbz [[REG2]],
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74 entry:
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75 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind
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76 %tmp = trunc i32 %vmaxv.i to i8
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77 %tobool = icmp eq i8 %tmp, 0
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78 br i1 %tobool, label %return, label %if.then
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79
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80 if.then:
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81 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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82 br label %return
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83
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84 return:
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85 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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86 ret i32 %retval.0
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87 }
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88
95
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89 define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
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90 ; CHECK-LABEL: test_vmaxv_u8_used_by_laneop:
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91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
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parents: 77
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92 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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93 ; CHECK-NEXT: ret
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94 entry:
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95 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
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96 %1 = trunc i32 %0 to i8
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97 %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
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98 ret <8 x i8> %2
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99 }
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100
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101 define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
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102 ; CHECK-LABEL: test_vmaxv_u16_used_by_laneop:
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parents: 77
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103 ; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
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parents: 77
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104 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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parents: 77
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105 ; CHECK-NEXT: ret
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106 entry:
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107 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2)
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108 %1 = trunc i32 %0 to i16
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109 %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
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110 ret <4 x i16> %2
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111 }
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112
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113 define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
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parents: 77
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114 ; CHECK-LABEL: test_vmaxv_u32_used_by_laneop:
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parents: 77
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115 ; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
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parents: 77
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116 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
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parents: 77
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117 ; CHECK-NEXT: ret
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118 entry:
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119 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2)
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120 %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
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121 ret <2 x i32> %1
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122 }
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123
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124 define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
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125 ; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop:
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126 ; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
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127 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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128 ; CHECK-NEXT: ret
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129 entry:
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130 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2)
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131 %1 = trunc i32 %0 to i8
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132 %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
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133 ret <16 x i8> %2
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134 }
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135
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136 define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
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137 ; CHECK-LABEL: test_vmaxvq_u16_used_by_laneop:
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138 ; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
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139 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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140 ; CHECK-NEXT: ret
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141 entry:
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142 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2)
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143 %1 = trunc i32 %0 to i16
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144 %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
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145 ret <8 x i16> %2
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146 }
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147
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148 define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
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149 ; CHECK-LABEL: test_vmaxvq_u32_used_by_laneop:
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150 ; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1
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151 ; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
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152 ; CHECK-NEXT: ret
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153 entry:
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154 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2)
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155 %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
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156 ret <4 x i32> %1
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157 }
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158
77
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159 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone
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160 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone
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161 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone
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162 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone
95
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163 declare i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32>) nounwind readnone
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164 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>) nounwind readnone