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annotate test/CodeGen/PowerPC/builtins-ppc-p8vector.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children
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120
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1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
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2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
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3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+power8-vector -mattr=-vsx < %s | FileCheck %s
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4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-VSX
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5
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6 @vsc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
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7 @vsc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
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8 @vuc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
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9 @vuc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
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10 @res_vll = common global <2 x i64> zeroinitializer, align 16
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11 @res_vull = common global <2 x i64> zeroinitializer, align 16
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12 @res_vsc = common global <16 x i8> zeroinitializer, align 16
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13 @res_vuc = common global <16 x i8> zeroinitializer, align 16
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14
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15 ; Function Attrs: nounwind
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16 define void @test1() {
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17 entry:
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18 %0 = load <16 x i8>, <16 x i8>* @vsc, align 16
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19 %1 = load <16 x i8>, <16 x i8>* @vsc2, align 16
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20 %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)
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21 store <2 x i64> %2, <2 x i64>* @res_vll, align 16
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22 ret void
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23 ; CHECK-LABEL: @test1
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24 ; CHECK: lvx [[REG1:[0-9]+]], 0, 3
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25 ; CHECK: lvx [[REG2:[0-9]+]], 0, 4
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26 ; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]
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27 ; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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28 }
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29
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30 ; Function Attrs: nounwind
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31 define void @test2() {
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32 entry:
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33 %0 = load <16 x i8>, <16 x i8>* @vuc, align 16
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34 %1 = load <16 x i8>, <16 x i8>* @vuc2, align 16
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35 %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)
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36 store <2 x i64> %2, <2 x i64>* @res_vull, align 16
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37 ret void
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38 ; CHECK-LABEL: @test2
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39 ; CHECK: lvx [[REG1:[0-9]+]], 0, 3
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40 ; CHECK: lvx [[REG2:[0-9]+]], 0, 4
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41 ; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]
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42 ; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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43 }
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44
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45 ; Function Attrs: nounwind
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46 define void @test3() {
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47 entry:
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48 %0 = load <16 x i8>, <16 x i8>* @vsc, align 16
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49 %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)
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50 store <16 x i8> %1, <16 x i8>* @res_vsc, align 16
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51 ret void
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52 ; CHECK-LABEL: @test3
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53 ; CHECK: lvx [[REG1:[0-9]+]],
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54 ; CHECK: vgbbd {{[0-9]+}}, [[REG1]]
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55 ; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}}
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56 }
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57
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58 ; Function Attrs: nounwind
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59 define void @test4() {
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60 entry:
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61 %0 = load <16 x i8>, <16 x i8>* @vuc, align 16
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62 %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)
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63 store <16 x i8> %1, <16 x i8>* @res_vuc, align 16
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64 ret void
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65 ; CHECK-LABEL: @test4
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66 ; CHECK: lvx [[REG1:[0-9]+]],
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67 ; CHECK: vgbbd {{[0-9]+}}, [[REG1]]
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68 ; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}}
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69 }
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70
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71 ; Function Attrs: nounwind readnone
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72 declare <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8>, <16 x i8>)
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73
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74 ; Function Attrs: nounwind readnone
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75 declare <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8>)