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annotate test/CodeGen/SystemZ/tdc-02.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
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120
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1 ; Test the Test Data Class instruction logic operation folding.
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2 ;
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3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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4
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5 declare i32 @llvm.s390.tdc.f32(float, i64)
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6 declare i32 @llvm.s390.tdc.f64(double, i64)
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7 declare i32 @llvm.s390.tdc.f128(fp128, i64)
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8
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9 ; Check using or i1
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10 define i32 @f1(float %x) {
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11 ; CHECK-LABEL: f1
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12 ; CHECK: tceb %f0, 7
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13 ; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
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14 ; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
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15 %a = call i32 @llvm.s390.tdc.f32(float %x, i64 3)
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16 %b = call i32 @llvm.s390.tdc.f32(float %x, i64 6)
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17 %a1 = icmp ne i32 %a, 0
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18 %b1 = icmp ne i32 %b, 0
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19 %res = or i1 %a1, %b1
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20 %xres = zext i1 %res to i32
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21 ret i32 %xres
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22 }
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23
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24 ; Check using and i1
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25 define i32 @f2(double %x) {
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26 ; CHECK-LABEL: f2
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27 ; CHECK: tcdb %f0, 2
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28 ; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
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29 ; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
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30 %a = call i32 @llvm.s390.tdc.f64(double %x, i64 3)
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31 %b = call i32 @llvm.s390.tdc.f64(double %x, i64 6)
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32 %a1 = icmp ne i32 %a, 0
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33 %b1 = icmp ne i32 %b, 0
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34 %res = and i1 %a1, %b1
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35 %xres = zext i1 %res to i32
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36 ret i32 %xres
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37 }
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38
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39 ; Check using xor i1
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40 define i32 @f3(fp128 %x) {
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41 ; CHECK-LABEL: f3
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42 ; CHECK: tcxb %f0, 5
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43 ; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
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44 ; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
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45 %a = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 3)
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46 %b = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 6)
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47 %a1 = icmp ne i32 %a, 0
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48 %b1 = icmp ne i32 %b, 0
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49 %res = xor i1 %a1, %b1
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50 %xres = zext i1 %res to i32
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51 ret i32 %xres
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52 }
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53
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54 ; Check using xor i1 - negated test
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55 define i32 @f4(fp128 %x) {
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56 ; CHECK-LABEL: f4
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57 ; CHECK: tcxb %f0, 4090
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58 ; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
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59 ; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
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60 %a = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 3)
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61 %b = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 6)
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62 %a1 = icmp ne i32 %a, 0
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63 %b1 = icmp eq i32 %b, 0
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64 %res = xor i1 %a1, %b1
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65 %xres = zext i1 %res to i32
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66 ret i32 %xres
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67 }
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68
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69 ; Check different first args
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70 define i32 @f5(float %x, float %y) {
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71 ; CHECK-LABEL: f5
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72 ; CHECK-NOT: tceb {{%f[0-9]+}}, 5
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73 ; CHECK-DAG: tceb %f0, 3
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74 ; CHECK-DAG: tceb %f2, 6
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75 %a = call i32 @llvm.s390.tdc.f32(float %x, i64 3)
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76 %b = call i32 @llvm.s390.tdc.f32(float %y, i64 6)
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77 %a1 = icmp ne i32 %a, 0
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78 %b1 = icmp ne i32 %b, 0
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79 %res = xor i1 %a1, %b1
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80 %xres = zext i1 %res to i32
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81 ret i32 %xres
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82 }
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83
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84 ; Non-const mask (not supported)
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85 define i32 @f6(float %x, i64 %y) {
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86 ; CHECK-LABEL: f6
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87 ; CHECK-DAG: tceb %f0, 0(%r2)
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88 ; CHECK-DAG: tceb %f0, 6
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89 %a = call i32 @llvm.s390.tdc.f32(float %x, i64 %y)
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90 %b = call i32 @llvm.s390.tdc.f32(float %x, i64 6)
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91 %a1 = icmp ne i32 %a, 0
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92 %b1 = icmp ne i32 %b, 0
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93 %res = xor i1 %a1, %b1
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94 %xres = zext i1 %res to i32
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95 ret i32 %xres
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96 }