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annotate test/CodeGen/X86/vec_setcc.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 60c9769439b8
children 3a76565eade5
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
120
1172e4bd9c6f update 4.0.0
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
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4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 define <16 x i8> @v16i8_icmp_uge(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
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7 ; SSE-LABEL: v16i8_icmp_uge:
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8 ; SSE: # BB#0:
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9 ; SSE-NEXT: pmaxub %xmm0, %xmm1
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10 ; SSE-NEXT: pcmpeqb %xmm1, %xmm0
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11 ; SSE-NEXT: retq
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12 ;
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13 ; AVX-LABEL: v16i8_icmp_uge:
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14 ; AVX: # BB#0:
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15 ; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
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16 ; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
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17 ; AVX-NEXT: retq
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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18 %1 = icmp uge <16 x i8> %a, %b
95c75e76d11b LLVM 3.4
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19 %2 = sext <16 x i1> %1 to <16 x i8>
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20 ret <16 x i8> %2
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21 }
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22
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23 define <16 x i8> @v16i8_icmp_ule(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
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24 ; SSE-LABEL: v16i8_icmp_ule:
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25 ; SSE: # BB#0:
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26 ; SSE-NEXT: pminub %xmm0, %xmm1
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27 ; SSE-NEXT: pcmpeqb %xmm1, %xmm0
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28 ; SSE-NEXT: retq
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29 ;
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30 ; AVX-LABEL: v16i8_icmp_ule:
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31 ; AVX: # BB#0:
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32 ; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm1
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33 ; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
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34 ; AVX-NEXT: retq
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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35 %1 = icmp ule <16 x i8> %a, %b
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36 %2 = sext <16 x i1> %1 to <16 x i8>
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37 ret <16 x i8> %2
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38 }
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39
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40 define <8 x i16> @v8i16_icmp_uge(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
120
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41 ; SSE2-LABEL: v8i16_icmp_uge:
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42 ; SSE2: # BB#0:
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43 ; SSE2-NEXT: psubusw %xmm0, %xmm1
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44 ; SSE2-NEXT: pxor %xmm0, %xmm0
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45 ; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
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46 ; SSE2-NEXT: retq
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47 ;
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48 ; SSE41-LABEL: v8i16_icmp_uge:
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49 ; SSE41: # BB#0:
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50 ; SSE41-NEXT: pmaxuw %xmm0, %xmm1
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51 ; SSE41-NEXT: pcmpeqw %xmm1, %xmm0
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52 ; SSE41-NEXT: retq
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53 ;
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54 ; AVX-LABEL: v8i16_icmp_uge:
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55 ; AVX: # BB#0:
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56 ; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1
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57 ; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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58 ; AVX-NEXT: retq
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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59 %1 = icmp uge <8 x i16> %a, %b
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60 %2 = sext <8 x i1> %1 to <8 x i16>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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61 ret <8 x i16> %2
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62 }
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63
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64 define <8 x i16> @v8i16_icmp_ule(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
120
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65 ; SSE2-LABEL: v8i16_icmp_ule:
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66 ; SSE2: # BB#0:
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67 ; SSE2-NEXT: psubusw %xmm1, %xmm0
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68 ; SSE2-NEXT: pxor %xmm1, %xmm1
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69 ; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
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70 ; SSE2-NEXT: retq
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71 ;
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72 ; SSE41-LABEL: v8i16_icmp_ule:
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73 ; SSE41: # BB#0:
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74 ; SSE41-NEXT: pminuw %xmm0, %xmm1
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75 ; SSE41-NEXT: pcmpeqw %xmm1, %xmm0
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76 ; SSE41-NEXT: retq
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77 ;
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78 ; AVX-LABEL: v8i16_icmp_ule:
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79 ; AVX: # BB#0:
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80 ; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm1
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81 ; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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82 ; AVX-NEXT: retq
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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83 %1 = icmp ule <8 x i16> %a, %b
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84 %2 = sext <8 x i1> %1 to <8 x i16>
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85 ret <8 x i16> %2
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86 }
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87
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88 define <4 x i32> @v4i32_icmp_uge(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
120
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89 ; SSE2-LABEL: v4i32_icmp_uge:
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90 ; SSE2: # BB#0:
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91 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
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92 ; SSE2-NEXT: pxor %xmm2, %xmm0
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93 ; SSE2-NEXT: pxor %xmm1, %xmm2
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94 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
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95 ; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
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96 ; SSE2-NEXT: pxor %xmm2, %xmm0
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97 ; SSE2-NEXT: retq
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98 ;
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99 ; SSE41-LABEL: v4i32_icmp_uge:
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100 ; SSE41: # BB#0:
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101 ; SSE41-NEXT: pmaxud %xmm0, %xmm1
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102 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
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103 ; SSE41-NEXT: retq
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104 ;
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105 ; AVX-LABEL: v4i32_icmp_uge:
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106 ; AVX: # BB#0:
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107 ; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm1
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108 ; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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109 ; AVX-NEXT: retq
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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110 %1 = icmp uge <4 x i32> %a, %b
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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111 %2 = sext <4 x i1> %1 to <4 x i32>
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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112 ret <4 x i32> %2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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113 }
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114
95c75e76d11b LLVM 3.4
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115 define <4 x i32> @v4i32_icmp_ule(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
120
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116 ; SSE2-LABEL: v4i32_icmp_ule:
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117 ; SSE2: # BB#0:
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118 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
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119 ; SSE2-NEXT: pxor %xmm2, %xmm1
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120 ; SSE2-NEXT: pxor %xmm2, %xmm0
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121 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
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122 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
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123 ; SSE2-NEXT: pxor %xmm1, %xmm0
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124 ; SSE2-NEXT: retq
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125 ;
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126 ; SSE41-LABEL: v4i32_icmp_ule:
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127 ; SSE41: # BB#0:
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128 ; SSE41-NEXT: pminud %xmm0, %xmm1
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129 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
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130 ; SSE41-NEXT: retq
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131 ;
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132 ; AVX-LABEL: v4i32_icmp_ule:
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133 ; AVX: # BB#0:
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134 ; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm1
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135 ; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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136 ; AVX-NEXT: retq
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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137 %1 = icmp ule <4 x i32> %a, %b
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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138 %2 = sext <4 x i1> %1 to <4 x i32>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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139 ret <4 x i32> %2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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140 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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141
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142 ; At one point we were incorrectly constant-folding a setcc to 0x1 instead of
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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143 ; 0xff, leading to a constpool load. The instruction doesn't matter here, but it
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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144 ; should set all bits to 1.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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145 define <16 x i8> @test_setcc_constfold_vi8(<16 x i8> %l, <16 x i8> %r) {
120
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146 ; SSE-LABEL: test_setcc_constfold_vi8:
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147 ; SSE: # BB#0:
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148 ; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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149 ; SSE-NEXT: retq
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150 ;
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151 ; AVX-LABEL: test_setcc_constfold_vi8:
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152 ; AVX: # BB#0:
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153 ; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
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154 ; AVX-NEXT: retq
0
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155 %test1 = icmp eq <16 x i8> %l, %r
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156 %mask1 = sext <16 x i1> %test1 to <16 x i8>
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157 %test2 = icmp ne <16 x i8> %l, %r
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158 %mask2 = sext <16 x i1> %test2 to <16 x i8>
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159 %res = or <16 x i8> %mask1, %mask2
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160 ret <16 x i8> %res
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161 }
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162
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163 ; Make sure sensible results come from doing extension afterwards
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164 define <16 x i8> @test_setcc_constfold_vi1(<16 x i8> %l, <16 x i8> %r) {
120
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165 ; SSE-LABEL: test_setcc_constfold_vi1:
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166 ; SSE: # BB#0:
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167 ; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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168 ; SSE-NEXT: retq
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169 ;
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170 ; AVX-LABEL: test_setcc_constfold_vi1:
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171 ; AVX: # BB#0:
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172 ; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
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173 ; AVX-NEXT: retq
0
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174 %test1 = icmp eq <16 x i8> %l, %r
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175 %test2 = icmp ne <16 x i8> %l, %r
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176 %res = or <16 x i1> %test1, %test2
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177 %mask = sext <16 x i1> %res to <16 x i8>
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178 ret <16 x i8> %mask
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179 }
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180
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181 ; 64-bit case is also particularly important, as the constant "-1" is probably
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182 ; just 32-bits wide.
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183 define <2 x i64> @test_setcc_constfold_vi64(<2 x i64> %l, <2 x i64> %r) {
120
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184 ; SSE-LABEL: test_setcc_constfold_vi64:
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185 ; SSE: # BB#0:
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186 ; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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187 ; SSE-NEXT: retq
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188 ;
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189 ; AVX-LABEL: test_setcc_constfold_vi64:
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190 ; AVX: # BB#0:
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191 ; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
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192 ; AVX-NEXT: retq
0
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193 %test1 = icmp eq <2 x i64> %l, %r
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194 %mask1 = sext <2 x i1> %test1 to <2 x i64>
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195 %test2 = icmp ne <2 x i64> %l, %r
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196 %mask2 = sext <2 x i1> %test2 to <2 x i64>
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197 %res = or <2 x i64> %mask1, %mask2
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198 ret <2 x i64> %res
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199 }