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annotate utils/TableGen/DisassemblerEmitter.cpp @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
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1 //===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 #include "CodeGenTarget.h"
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11 #include "X86DisassemblerTables.h"
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12 #include "X86RecognizableInstr.h"
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13 #include "llvm/TableGen/Error.h"
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14 #include "llvm/TableGen/Record.h"
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15 #include "llvm/TableGen/TableGenBackend.h"
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16
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17 using namespace llvm;
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18 using namespace llvm::X86Disassembler;
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19
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20 /// DisassemblerEmitter - Contains disassembler table emitters for various
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21 /// architectures.
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22
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23 /// X86 Disassembler Emitter
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24 ///
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25 /// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR
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26 /// THE END OF THIS COMMENT!
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27 ///
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28 /// The X86 disassembler emitter is part of the X86 Disassembler, which is
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29 /// documented in lib/Target/X86/X86Disassembler.h.
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30 ///
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31 /// The emitter produces the tables that the disassembler uses to translate
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32 /// instructions. The emitter generates the following tables:
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33 ///
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34 /// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to
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35 /// instruction contexts. Although for each attribute there are cases where
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36 /// that attribute determines decoding, in the majority of cases decoding is
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37 /// the same whether or not an attribute is present. For example, a 64-bit
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38 /// instruction with an OPSIZE prefix and an XS prefix decodes the same way in
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39 /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix
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40 /// may have effects on its execution, but does not change the instruction
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41 /// returned.) This allows considerable space savings in other tables.
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42 /// - Six tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM,
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43 /// THREEBYTEA6_SYM, and THREEBYTEA7_SYM contain the hierarchy that the
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44 /// decoder traverses while decoding an instruction. At the lowest level of
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45 /// this hierarchy are instruction UIDs, 16-bit integers that can be used to
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46 /// uniquely identify the instruction and correspond exactly to its position
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47 /// in the list of CodeGenInstructions for the target.
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48 /// - One table (INSTRUCTIONS_SYM) contains information about the operands of
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49 /// each instruction and how to decode them.
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50 ///
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51 /// During table generation, there may be conflicts between instructions that
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52 /// occupy the same space in the decode tables. These conflicts are resolved as
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53 /// follows in setTableFields() (X86DisassemblerTables.cpp)
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54 ///
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55 /// - If the current context is the native context for one of the instructions
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56 /// (that is, the attributes specified for it in the LLVM tables specify
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57 /// precisely the current context), then it has priority.
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58 /// - If the current context isn't native for either of the instructions, then
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59 /// the higher-priority context wins (that is, the one that is more specific).
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60 /// That hierarchy is determined by outranks() (X86DisassemblerTables.cpp)
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61 /// - If the current context is native for both instructions, then the table
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62 /// emitter reports a conflict and dies.
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63 ///
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64 /// *** RESOLUTION FOR "Primary decode conflict"S
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65 ///
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66 /// If two instructions collide, typically the solution is (in order of
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67 /// likelihood):
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68 ///
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69 /// (1) to filter out one of the instructions by editing filter()
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70 /// (X86RecognizableInstr.cpp). This is the most common resolution, but
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71 /// check the Intel manuals first to make sure that (2) and (3) are not the
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72 /// problem.
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73 /// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are
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74 /// accurate. Sometimes they are not.
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75 /// (3) to fix the tables to reflect the actual context (for example, required
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76 /// prefixes), and possibly to add a new context by editing
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77 /// lib/Target/X86/X86DisassemblerDecoderCommon.h. This is unlikely to be
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78 /// the cause.
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79 ///
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80 /// DisassemblerEmitter.cpp contains the implementation for the emitter,
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81 /// which simply pulls out instructions from the CodeGenTarget and pushes them
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82 /// into X86DisassemblerTables.
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83 /// X86DisassemblerTables.h contains the interface for the instruction tables,
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84 /// which manage and emit the structures discussed above.
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85 /// X86DisassemblerTables.cpp contains the implementation for the instruction
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86 /// tables.
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87 /// X86ModRMFilters.h contains filters that can be used to determine which
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88 /// ModR/M values are valid for a particular instruction. These are used to
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89 /// populate ModRMDecisions.
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90 /// X86RecognizableInstr.h contains the interface for a single instruction,
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91 /// which knows how to translate itself from a CodeGenInstruction and provide
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92 /// the information necessary for integration into the tables.
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93 /// X86RecognizableInstr.cpp contains the implementation for a single
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94 /// instruction.
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95
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96 namespace llvm {
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97
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98 extern void EmitFixedLenDecoder(RecordKeeper &RK, raw_ostream &OS,
120
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99 const std::string &PredicateNamespace,
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100 const std::string &GPrefix,
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101 const std::string &GPostfix,
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102 const std::string &ROK,
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103 const std::string &RFail, const std::string &L);
0
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104
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105 void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
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106 CodeGenTarget Target(Records);
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107 emitSourceFileHeader(" * " + Target.getName() + " Disassembler", OS);
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108
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109 // X86 uses a custom disassembler.
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110 if (Target.getName() == "X86") {
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111 DisassemblerTables Tables;
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112
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113 ArrayRef<const CodeGenInstruction*> numberedInstructions =
0
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114 Target.getInstructionsByEnumValue();
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115
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116 for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i)
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117 RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i);
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118
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119 if (Tables.hasConflicts()) {
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120 PrintError(Target.getTargetRecord()->getLoc(), "Primary decode conflict");
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121 return;
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122 }
0
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123
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124 Tables.emit(OS);
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125 return;
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126 }
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127
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128 // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses.
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129 if (Target.getName() == "ARM" || Target.getName() == "Thumb" ||
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130 Target.getName() == "AArch64" || Target.getName() == "ARM64") {
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131 std::string PredicateNamespace = Target.getName();
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132 if (PredicateNamespace == "Thumb")
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133 PredicateNamespace = "ARM";
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134
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135 EmitFixedLenDecoder(Records, OS, PredicateNamespace,
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136 "if (!Check(S, ", "))",
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137 "S", "MCDisassembler::Fail",
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138 " MCDisassembler::DecodeStatus S = "
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139 "MCDisassembler::Success;\n(void)S;");
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140 return;
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141 }
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142
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143 EmitFixedLenDecoder(Records, OS, Target.getName(),
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144 "if (", " == MCDisassembler::Fail)",
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145 "MCDisassembler::Success", "MCDisassembler::Fail", "");
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146 }
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147
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148 } // End llvm namespace