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annotate llvm/test/Transforms/IndVarSimplify/eliminate-sat.ll @ 252:1f2b6ac9f198 llvm-original

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LLVM16-1
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Fri, 18 Aug 2023 09:04:13 +0900
parents 1d019706d866
children
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1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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1f2b6ac9f198 LLVM16-1
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2 ; RUN: opt < %s -S -passes=indvars | FileCheck %s
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3
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4 declare i32 @llvm.uadd.sat.i32(i32, i32)
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5 declare i32 @llvm.sadd.sat.i32(i32, i32)
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6 declare i32 @llvm.usub.sat.i32(i32, i32)
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7 declare i32 @llvm.ssub.sat.i32(i32, i32)
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8
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9 define void @uadd_sat(ptr %p) {
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10 ; CHECK-LABEL: @uadd_sat(
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11 ; CHECK-NEXT: entry:
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12 ; CHECK-NEXT: br label [[LOOP:%.*]]
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13 ; CHECK: loop:
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14 ; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[LOOP]] ]
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15 ; CHECK-NEXT: [[SAT1:%.*]] = add nuw nsw i32 [[I]], 1
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16 ; CHECK-NEXT: store volatile i32 [[SAT1]], ptr [[P:%.*]]
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17 ; CHECK-NEXT: [[I_INC]] = add nuw nsw i32 [[I]], 1
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18 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[I_INC]], 100
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19 ; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[END:%.*]]
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20 ; CHECK: end:
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21 ; CHECK-NEXT: ret void
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22 ;
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23 entry:
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24 br label %loop
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25
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26 loop:
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27 %i = phi i32 [ 0, %entry ], [ %i.inc, %loop ]
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28 %sat = call i32 @llvm.uadd.sat.i32(i32 %i, i32 1)
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29 store volatile i32 %sat, ptr %p
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30 %i.inc = add nuw nsw i32 %i, 1
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31 %cmp = icmp ne i32 %i.inc, 100
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32 br i1 %cmp, label %loop, label %end
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33
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34 end:
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35 ret void
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36 }
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37
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38 define void @sadd_sat(ptr %p) {
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39 ; CHECK-LABEL: @sadd_sat(
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40 ; CHECK-NEXT: entry:
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41 ; CHECK-NEXT: br label [[LOOP:%.*]]
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42 ; CHECK: loop:
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43 ; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[LOOP]] ]
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44 ; CHECK-NEXT: [[SAT1:%.*]] = add nuw nsw i32 [[I]], 1
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45 ; CHECK-NEXT: store volatile i32 [[SAT1]], ptr [[P:%.*]]
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46 ; CHECK-NEXT: [[I_INC]] = add nuw nsw i32 [[I]], 1
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47 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[I_INC]], 100
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48 ; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[END:%.*]]
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49 ; CHECK: end:
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50 ; CHECK-NEXT: ret void
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51 ;
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52 entry:
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53 br label %loop
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54
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55 loop:
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56 %i = phi i32 [ 0, %entry ], [ %i.inc, %loop ]
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57 %sat = call i32 @llvm.sadd.sat.i32(i32 %i, i32 1)
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58 store volatile i32 %sat, ptr %p
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59 %i.inc = add nuw nsw i32 %i, 1
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60 %cmp = icmp ne i32 %i.inc, 100
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61 br i1 %cmp, label %loop, label %end
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62
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63 end:
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64 ret void
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65 }
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66
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67 define void @usub_sat(ptr %p) {
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68 ; CHECK-LABEL: @usub_sat(
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69 ; CHECK-NEXT: entry:
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70 ; CHECK-NEXT: br label [[LOOP:%.*]]
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71 ; CHECK: loop:
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72 ; CHECK-NEXT: [[I:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[LOOP]] ]
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73 ; CHECK-NEXT: [[SAT1:%.*]] = sub nuw nsw i32 [[I]], 1
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74 ; CHECK-NEXT: store volatile i32 [[SAT1]], ptr [[P:%.*]]
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75 ; CHECK-NEXT: [[I_INC]] = add nuw nsw i32 [[I]], 1
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76 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[I_INC]], 100
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77 ; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[END:%.*]]
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78 ; CHECK: end:
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79 ; CHECK-NEXT: ret void
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80 ;
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81 entry:
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82 br label %loop
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83
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84 loop:
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85 %i = phi i32 [ 1, %entry ], [ %i.inc, %loop ]
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86 %sat = call i32 @llvm.usub.sat.i32(i32 %i, i32 1)
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87 store volatile i32 %sat, ptr %p
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88 %i.inc = add nuw nsw i32 %i, 1
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89 %cmp = icmp ne i32 %i.inc, 100
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90 br i1 %cmp, label %loop, label %end
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91
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92 end:
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93 ret void
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94 }
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95
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96 define void @ssub_sat(ptr %p) {
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97 ; CHECK-LABEL: @ssub_sat(
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98 ; CHECK-NEXT: entry:
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99 ; CHECK-NEXT: br label [[LOOP:%.*]]
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100 ; CHECK: loop:
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101 ; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[LOOP]] ]
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102 ; CHECK-NEXT: [[SAT1:%.*]] = sub nsw i32 [[I]], 1
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103 ; CHECK-NEXT: store volatile i32 [[SAT1]], ptr [[P:%.*]]
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104 ; CHECK-NEXT: [[I_INC]] = add nuw nsw i32 [[I]], 1
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105 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[I_INC]], 100
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106 ; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[END:%.*]]
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107 ; CHECK: end:
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108 ; CHECK-NEXT: ret void
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109 ;
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110 entry:
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111 br label %loop
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112
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113 loop:
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114 %i = phi i32 [ 0, %entry ], [ %i.inc, %loop ]
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115 %sat = call i32 @llvm.ssub.sat.i32(i32 %i, i32 1)
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116 store volatile i32 %sat, ptr %p
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117 %i.inc = add nuw nsw i32 %i, 1
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118 %cmp = icmp ne i32 %i.inc, 100
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119 br i1 %cmp, label %loop, label %end
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120
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121 end:
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122 ret void
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123 }