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1 // REQUIRES: arm-registered-target
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2 // RUN: %clang_cc1 -triple armv8.3a-arm-none-eabi -target-cpu generic \
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3 // RUN: -target-feature +fullfp16 -mfloat-abi soft -S -emit-llvm -o - %s | \
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4 // RUN: opt -S -sroa -o - | FileCheck %s
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5
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6 #include <arm_neon.h>
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7
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8 void foo16x4_rot90(float16x4_t a, float16x4_t b)
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9 {
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10 // CHECK: call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16
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11 float16x4_t result = vcadd_rot90_f16(a, b);
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12 }
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13
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14 void foo32x2_rot90(float32x2_t a, float32x2_t b)
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15 {
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16 // CHECK: call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32
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17 float32x2_t result = vcadd_rot90_f32(a, b);
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18 }
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19
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20 void foo16x8_rot90(float16x8_t a, float16x8_t b)
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21 {
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22 // CHECK: call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16
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23 float16x8_t result = vcaddq_rot90_f16(a, b);
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24 }
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25
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26 void foo32x4_rot90(float32x4_t a, float32x4_t b)
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27 {
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28 // CHECK: call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32
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29 float32x4_t result = vcaddq_rot90_f32(a, b);
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30 }
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31
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32 void foo16x4_rot270(float16x4_t a, float16x4_t b)
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33 {
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34 // CHECK: call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16
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35 float16x4_t result = vcadd_rot270_f16(a, b);
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36 }
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37
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38 void foo32x2_rot270(float32x2_t a, float32x2_t b)
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39 {
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40 // CHECK: call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32
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41 float32x2_t result = vcadd_rot270_f32(a, b);
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42 }
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43
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44 void foo16x8_rot270(float16x8_t a, float16x8_t b)
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45 {
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46 // CHECK: call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16
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47 float16x8_t result = vcaddq_rot270_f16(a, b);
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48 }
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49
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50 void foo32x4_rot270(float32x4_t a, float32x4_t b)
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51 {
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52 // CHECK: call <4 x float> @llvm.arm.neon.vcadd.rot270.v4f32
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53 float32x4_t result = vcaddq_rot270_f32(a, b);
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54 }
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