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150
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1 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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2
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3 ; GCN-LABEL: {{^}}select_and1:
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207
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4 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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5 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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150
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6 ; GCN-NOT: v_and_b32
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207
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7 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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150
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8 define amdgpu_kernel void @select_and1(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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9 %c = icmp slt i32 %x, 11
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10 %s = select i1 %c, i32 0, i32 -1
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11 %a = and i32 %y, %s
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12 store i32 %a, i32 addrspace(1)* %p, align 4
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13 ret void
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14 }
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15
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16 ; GCN-LABEL: {{^}}select_and2:
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207
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17 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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18 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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150
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19 ; GCN-NOT: v_and_b32
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207
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20 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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150
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21 define amdgpu_kernel void @select_and2(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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22 %c = icmp slt i32 %x, 11
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23 %s = select i1 %c, i32 0, i32 -1
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24 %a = and i32 %s, %y
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25 store i32 %a, i32 addrspace(1)* %p, align 4
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26 ret void
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27 }
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28
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29 ; GCN-LABEL: {{^}}select_and3:
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207
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30 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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31 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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150
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32 ; GCN-NOT: v_and_b32
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207
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33 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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150
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34 define amdgpu_kernel void @select_and3(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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35 %c = icmp slt i32 %x, 11
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36 %s = select i1 %c, i32 -1, i32 0
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37 %a = and i32 %y, %s
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38 store i32 %a, i32 addrspace(1)* %p, align 4
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39 ret void
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40 }
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41
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42 ; GCN-LABEL: {{^}}select_and_v4:
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43 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}},
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44 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}},
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45 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}},
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46 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}},
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47 ; GCN-NOT: v_and_b32
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48 ; GCN: store_dword
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49 define amdgpu_kernel void @select_and_v4(<4 x i32> addrspace(1)* %p, i32 %x, <4 x i32> %y) {
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50 %c = icmp slt i32 %x, 11
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51 %s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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52 %a = and <4 x i32> %s, %y
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53 store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32
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54 ret void
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55 }
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56
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57 ; GCN-LABEL: {{^}}select_or1:
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207
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58 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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59 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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150
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60 ; GCN-NOT: v_or_b32
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207
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61 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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150
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62 define amdgpu_kernel void @select_or1(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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63 %c = icmp slt i32 %x, 11
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64 %s = select i1 %c, i32 0, i32 -1
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65 %a = or i32 %y, %s
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66 store i32 %a, i32 addrspace(1)* %p, align 4
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67 ret void
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68 }
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69
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70 ; GCN-LABEL: {{^}}select_or2:
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207
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71 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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72 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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150
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73 ; GCN-NOT: v_or_b32
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207
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74 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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150
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75 define amdgpu_kernel void @select_or2(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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76 %c = icmp slt i32 %x, 11
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77 %s = select i1 %c, i32 0, i32 -1
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78 %a = or i32 %s, %y
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79 store i32 %a, i32 addrspace(1)* %p, align 4
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80 ret void
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81 }
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82
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83 ; GCN-LABEL: {{^}}select_or3:
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207
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84 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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85 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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150
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86 ; GCN-NOT: v_or_b32
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207
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87 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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150
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88 define amdgpu_kernel void @select_or3(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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89 %c = icmp slt i32 %x, 11
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90 %s = select i1 %c, i32 -1, i32 0
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91 %a = or i32 %y, %s
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92 store i32 %a, i32 addrspace(1)* %p, align 4
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93 ret void
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94 }
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95
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96 ; GCN-LABEL: {{^}}select_or_v4:
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97 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}},
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98 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}},
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99 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}},
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100 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}},
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101 ; GCN-NOT: v_or_b32
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102 ; GCN: store_dword
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103 define amdgpu_kernel void @select_or_v4(<4 x i32> addrspace(1)* %p, i32 %x, <4 x i32> %y) {
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104 %c = icmp slt i32 %x, 11
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105 %s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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106 %a = or <4 x i32> %s, %y
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107 store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32
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108 ret void
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109 }
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110
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111 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants:
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207
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112 ; GCN: s_cselect_b32 s{{[0-9]+}}, 9, 2
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150
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113 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
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114 %sel = select i1 %cond, i32 -4, i32 3
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115 %bo = sub i32 5, %sel
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116 store i32 %bo, i32 addrspace(1)* %p, align 4
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117 ret void
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118 }
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119
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120 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_i16:
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207
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121 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9,
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150
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122 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16(i16 addrspace(1)* %p, i1 %cond) {
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123 %sel = select i1 %cond, i16 -4, i16 3
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124 %bo = sub i16 5, %sel
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125 store i16 %bo, i16 addrspace(1)* %p, align 2
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126 ret void
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127 }
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128
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129 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_i16_neg:
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130 ; GCN: v_mov_b32_e32 [[F:v[0-9]+]], 0xfffff449
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131 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, [[F]], -3,
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132 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16_neg(i16 addrspace(1)* %p, i1 %cond) {
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133 %sel = select i1 %cond, i16 4, i16 3000
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134 %bo = sub i16 1, %sel
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135 store i16 %bo, i16 addrspace(1)* %p, align 2
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136 ret void
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137 }
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138
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139 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_v2i16:
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207
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140 ; GCN-DAG: s_mov_b32 [[T:s[0-9]+]], 0x50009
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141 ; GCN: s_cselect_b32 s{{[0-9]+}}, [[T]], 0x60002
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150
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142 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v2i16(<2 x i16> addrspace(1)* %p, i1 %cond) {
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143 %sel = select i1 %cond, <2 x i16> <i16 -4, i16 2>, <2 x i16> <i16 3, i16 1>
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144 %bo = sub <2 x i16> <i16 5, i16 7>, %sel
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145 store <2 x i16> %bo, <2 x i16> addrspace(1)* %p, align 4
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146 ret void
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147 }
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148
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149 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_v4i32:
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150 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9,
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151 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 6, 5,
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152 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 10, 6,
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153 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 14, 7,
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154 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v4i32(<4 x i32> addrspace(1)* %p, i1 %cond) {
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155 %sel = select i1 %cond, <4 x i32> <i32 -4, i32 2, i32 3, i32 4>, <4 x i32> <i32 3, i32 1, i32 -1, i32 -3>
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156 %bo = sub <4 x i32> <i32 5, i32 7, i32 9, i32 11>, %sel
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157 store <4 x i32> %bo, <4 x i32> addrspace(1)* %p, align 32
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158 ret void
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159 }
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160
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161 ; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i64:
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207
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162 ; GCN: s_cselect_b32 s{{[0-9]+}}, 0, 5
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150
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163 define amdgpu_kernel void @sdiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) {
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164 %sel = select i1 %cond, i64 121, i64 23
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165 %bo = sdiv i64 120, %sel
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166 store i64 %bo, i64 addrspace(1)* %p, align 8
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167 ret void
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168 }
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169
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170 ; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i32:
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207
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171 ; GCN: s_cselect_b32 s{{[0-9]+}}, 26, 8
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150
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172 define amdgpu_kernel void @sdiv_constant_sel_constants_i32(i32 addrspace(1)* %p, i1 %cond) {
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173 %sel = select i1 %cond, i32 7, i32 23
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174 %bo = sdiv i32 184, %sel
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175 store i32 %bo, i32 addrspace(1)* %p, align 8
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176 ret void
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177 }
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178
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179 ; GCN-LABEL: {{^}}udiv_constant_sel_constants_i64:
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207
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180 ; GCN: s_cselect_b32 s{{[0-9]+}}, 0, 5
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150
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181 define amdgpu_kernel void @udiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) {
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182 %sel = select i1 %cond, i64 -4, i64 23
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183 %bo = udiv i64 120, %sel
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184 store i64 %bo, i64 addrspace(1)* %p, align 8
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185 ret void
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186 }
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187
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188 ; GCN-LABEL: {{^}}srem_constant_sel_constants:
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207
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189 ; GCN: s_cselect_b32 s{{[0-9]+}}, 33, 3
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150
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190 define amdgpu_kernel void @srem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) {
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191 %sel = select i1 %cond, i64 34, i64 15
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192 %bo = srem i64 33, %sel
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193 store i64 %bo, i64 addrspace(1)* %p, align 8
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194 ret void
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195 }
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196
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197 ; GCN-LABEL: {{^}}urem_constant_sel_constants:
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207
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198 ; GCN: s_cselect_b32 s{{[0-9]+}}, 33, 3
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150
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199 define amdgpu_kernel void @urem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) {
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200 %sel = select i1 %cond, i64 34, i64 15
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201 %bo = urem i64 33, %sel
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202 store i64 %bo, i64 addrspace(1)* %p, align 8
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203 ret void
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204 }
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205
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206 ; GCN-LABEL: {{^}}shl_constant_sel_constants:
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207
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207 ; GCN: s_cselect_b32 s{{[0-9]+}}, 4, 8
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150
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208 define amdgpu_kernel void @shl_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
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209 %sel = select i1 %cond, i32 2, i32 3
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210 %bo = shl i32 1, %sel
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211 store i32 %bo, i32 addrspace(1)* %p, align 4
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212 ret void
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213 }
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214
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215 ; GCN-LABEL: {{^}}lshr_constant_sel_constants:
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207
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216 ; GCN: s_cselect_b32 s{{[0-9]+}}, 16, 8
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150
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217 define amdgpu_kernel void @lshr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
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218 %sel = select i1 %cond, i32 2, i32 3
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219 %bo = lshr i32 64, %sel
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220 store i32 %bo, i32 addrspace(1)* %p, align 4
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221 ret void
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222 }
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223
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224 ; GCN-LABEL: {{^}}ashr_constant_sel_constants:
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207
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225 ; GCN: s_cselect_b32 s{{[0-9]+}}, 32, 16
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150
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226 define amdgpu_kernel void @ashr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
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227 %sel = select i1 %cond, i32 2, i32 3
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228 %bo = ashr i32 128, %sel
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229 store i32 %bo, i32 addrspace(1)* %p, align 4
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230 ret void
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231 }
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232
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233 ; GCN-LABEL: {{^}}fsub_constant_sel_constants:
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234 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, -4.0, 1.0,
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235 define amdgpu_kernel void @fsub_constant_sel_constants(float addrspace(1)* %p, i1 %cond) {
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236 %sel = select i1 %cond, float -2.0, float 3.0
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237 %bo = fsub float -1.0, %sel
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238 store float %bo, float addrspace(1)* %p, align 4
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239 ret void
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240 }
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241
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242 ; GCN-LABEL: {{^}}fsub_constant_sel_constants_f16:
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243 ; TODO: it shall be possible to fold constants with OpSel
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244 ; GCN-DAG: v_mov_b32_e32 [[T:v[0-9]+]], 0x3c00
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245 ; GCN-DAG: v_mov_b32_e32 [[F:v[0-9]+]], 0xc400
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246 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, [[F]], [[T]],
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247 define amdgpu_kernel void @fsub_constant_sel_constants_f16(half addrspace(1)* %p, i1 %cond) {
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248 %sel = select i1 %cond, half -2.0, half 3.0
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249 %bo = fsub half -1.0, %sel
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250 store half %bo, half addrspace(1)* %p, align 2
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251 ret void
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252 }
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253
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254 ; GCN-LABEL: {{^}}fsub_constant_sel_constants_v2f16:
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207
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255 ; GCN: s_cselect_b32 s{{[0-9]+}}, 0x45003c00, -2.0
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150
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256 define amdgpu_kernel void @fsub_constant_sel_constants_v2f16(<2 x half> addrspace(1)* %p, i1 %cond) {
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257 %sel = select i1 %cond, <2 x half> <half -2.0, half -3.0>, <2 x half> <half -1.0, half 4.0>
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258 %bo = fsub <2 x half> <half -1.0, half 2.0>, %sel
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259 store <2 x half> %bo, <2 x half> addrspace(1)* %p, align 4
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260 ret void
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261 }
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262
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263 ; GCN-LABEL: {{^}}fsub_constant_sel_constants_v4f32:
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264 ; GCN-DAG: v_mov_b32_e32 [[T2:v[0-9]+]], 0x40a00000
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265 ; GCN-DAG: v_mov_b32_e32 [[T3:v[0-9]+]], 0x41100000
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266 ; GCN-DAG: v_mov_b32_e32 [[T4:v[0-9]+]], 0x41500000
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267 ; GCN-DAG: v_mov_b32_e32 [[F4:v[0-9]+]], 0x40c00000
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268 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0,
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269 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2.0, [[T2]],
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270 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 4.0, [[T3]],
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271 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, [[F4]], [[T4]],
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272 define amdgpu_kernel void @fsub_constant_sel_constants_v4f32(<4 x float> addrspace(1)* %p, i1 %cond) {
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273 %sel = select i1 %cond, <4 x float> <float -2.0, float -3.0, float -4.0, float -5.0>, <4 x float> <float -1.0, float 0.0, float 1.0, float 2.0>
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274 %bo = fsub <4 x float> <float -1.0, float 2.0, float 5.0, float 8.0>, %sel
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275 store <4 x float> %bo, <4 x float> addrspace(1)* %p, align 32
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276 ret void
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277 }
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278
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279 ; GCN-LABEL: {{^}}fdiv_constant_sel_constants:
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280 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 4.0, -2.0,
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281 define amdgpu_kernel void @fdiv_constant_sel_constants(float addrspace(1)* %p, i1 %cond) {
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282 %sel = select i1 %cond, float -4.0, float 2.0
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283 %bo = fdiv float 8.0, %sel
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284 store float %bo, float addrspace(1)* %p, align 4
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285 ret void
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286 }
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287
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288 ; GCN-LABEL: {{^}}frem_constant_sel_constants:
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289 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0,
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290 define amdgpu_kernel void @frem_constant_sel_constants(float addrspace(1)* %p, i1 %cond) {
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291 %sel = select i1 %cond, float -4.0, float 3.0
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292 %bo = frem float 5.0, %sel
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293 store float %bo, float addrspace(1)* %p, align 4
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294 ret void
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295 }
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