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1 // RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | \
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2 // RUN: FileCheck --check-prefix=DISASS %s
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3 // RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | \
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4 // RUN: FileCheck --check-prefix=MATCHER %s
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5 // RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | \
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6 // RUN: FileCheck --check-prefix=WRITER %s
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7
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8 // Check that combining conditions in AssemblerPredicate generates the correct
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9 // output when using both the (all_of) AND operator, and the (any_of) OR
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10 // operator.
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11
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12 include "llvm/Target/Target.td"
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13
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14 def archInstrInfo : InstrInfo { }
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15 def archAsmWriter : AsmWriter {
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16 int PassSubtarget = 1;
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17 }
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18
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19 def arch : Target {
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20 let InstructionSet = archInstrInfo;
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21 let AssemblyWriters = [archAsmWriter];
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22 }
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23
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24 let Namespace = "arch" in {
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25 def R0 : Register<"r0">;
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26 def R1 : Register<"r1">;
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27 def R2 : Register<"r2">;
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28 def R3 : Register<"r3">;
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29 def R4 : Register<"r4">;
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30 }
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31 def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3, R4)>;
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32
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33 class TestInsn<int Opc, list<Predicate> Preds> : Instruction {
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34 let Size = 2;
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35 let OutOperandList = (outs);
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36 let InOperandList = (ins Regs:$r);
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37 field bits<16> Inst;
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38 let Inst = Opc;
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39 let AsmString = NAME # " $r";
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40 field bits<16> SoftFail = 0;
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41 let Predicates = Preds;
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42 }
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43
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44
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45 def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
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46 def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
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47 def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
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48 def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
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49 def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
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50
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51 def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
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52 def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
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53 def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
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54 // MATCHER: if (FB[arch::AsmCond1])
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55 // MATCHER-NEXT: Features.set(Feature_AsmPred1Bit);
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56 // MATCHER-NEXT: if (FB[arch::AsmCond2a] && FB[arch::AsmCond2b])
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57 // MATCHER-NEXT: Features.set(Feature_AsmPred2Bit);
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58 // MATCHER-NEXT: if ((FB[arch::AsmCond3a] || FB[arch::AsmCond3b]))
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59 // MATCHER-NEXT: Features.set(Feature_AsmPred3Bit);
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60
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61 def insn1 : TestInsn<1, [AsmPred1]>;
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62 // DISASS: return (Bits[arch::AsmCond1]);
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63
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64 def insn2 : TestInsn<2, [AsmPred2]>;
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65 // DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
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66
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67 def insn3 : TestInsn<3, [AsmPred3]>;
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68 // DISASS: return ((Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
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69
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70 def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>;
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71 // DISASS: return (Bits[arch::AsmCond1] && Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
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72
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73 def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>;
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74 // DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
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75
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76 def insn6 : TestInsn<6, []>;
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77 def : InstAlias<"alias1", (insn6 R0)> { let Predicates = [AsmPred1]; }
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78 // WRITER: // (insn6 R0)
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79 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R0},
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80 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
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81 def : InstAlias<"alias2", (insn6 R1)> { let Predicates = [AsmPred2]; }
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82 // WRITER: // (insn6 R1)
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83 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R1},
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84 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a},
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85 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b},
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86 def : InstAlias<"alias3", (insn6 R2)> { let Predicates = [AsmPred3]; }
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87 // WRITER: // (insn6 R2)
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88 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R2},
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89 // WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a},
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90 // WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b},
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91 // WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0},
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92 def : InstAlias<"alias4", (insn6 R3)> { let Predicates = [AsmPred1, AsmPred2]; }
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93 // WRITER: // (insn6 R3)
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94 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R3},
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95 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
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96 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a},
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97 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b},
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98 def : InstAlias<"alias5", (insn6 R4)> { let Predicates = [AsmPred1, AsmPred3]; }
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99 // WRITER: // (insn6 R4)
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100 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R4},
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101 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
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102 // WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a},
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103 // WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b},
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104 // WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0},
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