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annotate llvm/test/TableGen/dag-isel-res-order.td @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 1d019706d866
children
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1 // RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
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2
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3 include "llvm/Target/Target.td"
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4
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5 def TestTargetInstrInfo : InstrInfo;
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6
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7 def TestTarget : Target {
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8 let InstructionSet = TestTargetInstrInfo;
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9 }
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10
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11 def REG : Register<"REG">;
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12 def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
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13
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14 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::UDIVREM)
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15 // CHECK: OPC_EmitNode2, TARGET_VAL(::INSTR)
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16 // CHECK: Results = #2 #3
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17 // CHECK: OPC_CompleteMatch, 2, 3, 2
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18 def INSTR : Instruction {
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19 let OutOperandList = (outs GPR:$r1, GPR:$r0);
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20 let InOperandList = (ins GPR:$t0, GPR:$t1);
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21 let Pattern = [(set i32:$r0, i32:$r1, (udivrem i32:$t0, i32:$t1))];
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22 }