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annotate llvm/test/TableGen/inhibit-pset.td @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 0572611fdcc8
children c4bab56944e8
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1 // RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
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2
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3 include "reg-with-subregs-common.td"
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4
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5 // CHECK-DAG: GPR32_AND_XR32RegClassID =
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6 // CHECK-DAG: XR32RegClassID =
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7
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8 def X0 : Register <"x0">;
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9
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10 // CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
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11 // CHECK-NEXT: static const char *const PressureNameTable[] = {
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12 // CHECK-NEXT: "GPR32",
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13 // CHECK-NEXT: };
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14 // CHECK-NEXT: return PressureNameTable[Idx];
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15 // CHECK-NEXT: }
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16
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17 // CHECK: unsigned TestTargetGenRegisterInfo::
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18 // CHECK-NEXT: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
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19 // CHECK-NEXT: static const uint16_t PressureLimitTable[] = {
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20 // CHECK-NEXT: {{[0-9]+}}, // 0: GPR32
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21 // CHECK-NEXT: };
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22 // CHECK-NEXT: return PressureLimitTable[Idx];
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23 // CHECK-NEXT:}
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24
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25 // CHECK: static const int RCSetsTable[] = {
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26 // CHECK-NEXT: /* 0 */ 0, -1,
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27 // CHECK-NEXT: };
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28
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29 def XR32 : RegisterClass<"TestTarget", [i32], 32, (add X0)> {
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30 let GeneratePressureSet = 0;
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31 }
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32
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33 def GPR32_AND_XR32 : RegisterClass<"TestTarget", [i32], 32, (add GPR32, X0)>;