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1 //===-- AVRInstrInfo.td - AVR Instruction Formats ----------*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // AVR Instruction Format Definitions.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 // A generic AVR instruction.
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15 class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction
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16 {
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17 let Namespace = "AVR";
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18
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19 dag OutOperandList = outs;
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20 dag InOperandList = ins;
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21 let AsmString = asmstr;
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22 let Pattern = pattern;
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23
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24 field bits<32> SoftFail = 0;
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25 }
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26
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27 /// A 16-bit AVR instruction.
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28 class AVRInst16<dag outs, dag ins, string asmstr, list<dag> pattern>
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29 : AVRInst<outs, ins, asmstr, pattern>
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30 {
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31 field bits<16> Inst;
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32
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33 let Size = 2;
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34 }
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35
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36 /// a 32-bit AVR instruction.
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37 class AVRInst32<dag outs, dag ins, string asmstr, list<dag> pattern>
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38 : AVRInst<outs, ins, asmstr, pattern>
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39 {
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40 field bits<32> Inst;
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41
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42 let Size = 4;
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43 }
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44
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45 // A class for pseudo instructions.
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46 // Psuedo instructions are not real AVR instructions. The DAG stores
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47 // psuedo instructions which are replaced by real AVR instructions by
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48 // AVRExpandPseudoInsts.cpp.
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49 //
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50 // For example, the ADDW (add wide, as in add 16 bit values) instruction
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51 // is defined as a pseudo instruction. In AVRExpandPseudoInsts.cpp,
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52 // the instruction is then replaced by two add instructions - one for each byte.
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53 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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54 : AVRInst16<outs, ins, asmstr, pattern>
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55 {
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56 let Pattern = pattern;
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57
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58 let isPseudo = 1;
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59 let isCodeGenOnly = 1;
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60 }
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61
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62 //===----------------------------------------------------------------------===//
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63 // Register / register instruction: <|opcode|ffrd|dddd|rrrr|>
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64 // opcode = 4 bits.
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65 // f = secondary opcode = 2 bits
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66 // d = destination = 5 bits
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67 // r = source = 5 bits
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68 // (Accepts all registers)
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69 //===----------------------------------------------------------------------===//
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70 class FRdRr<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
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71 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
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72 {
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73 bits<5> rd;
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74 bits<5> rr;
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75
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76 let Inst{15-12} = opcode;
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77 let Inst{11-10} = f;
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78 let Inst{9} = rr{4};
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79 let Inst{8-4} = rd;
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80 let Inst{3-0} = rr{3-0};
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81 }
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82
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83 class FTST<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
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84 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
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85 {
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86 bits<5> rd;
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87
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88 let Inst{15-12} = opcode;
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89 let Inst{11-10} = f;
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90 let Inst{9} = rd{4};
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91 let Inst{8-4} = rd;
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92 let Inst{3-0} = rd{3-0};
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93 }
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94
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95 //===----------------------------------------------------------------------===//
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96 // Instruction of the format `<mnemonic> Z, Rd`
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97 // <|1001|001r|rrrr|0ttt>
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98 //===----------------------------------------------------------------------===//
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99 class FZRd<bits<3> t, dag outs, dag ins, string asmstr, list<dag> pattern>
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100 : AVRInst16<outs, ins, asmstr, pattern>
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101 {
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102 bits<5> rd;
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103
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104 let Inst{15-12} = 0b1001;
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105
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106 let Inst{11-9} = 0b001;
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107 let Inst{8} = rd{4};
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108
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109 let Inst{7-4} = rd{3-0};
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110
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111 let Inst{3} = 0;
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112 let Inst{2-0} = t;
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113 }
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114
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115 //===----------------------------------------------------------------------===//
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116 // Register / immediate8 instruction: <|opcode|KKKK|dddd|KKKK|>
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117 // opcode = 4 bits.
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118 // K = constant data = 8 bits
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119 // d = destination = 4 bits
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120 // (Only accepts r16-r31)
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121 //===----------------------------------------------------------------------===//
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122 class FRdK<bits<4> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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123 : AVRInst16<outs, ins, asmstr, pattern>
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124 {
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125 bits<4> rd;
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126 bits<8> k;
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127
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128 let Inst{15-12} = opcode;
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129 let Inst{11-8} = k{7-4};
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130 let Inst{7-4} = rd{3-0};
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131 let Inst{3-0} = k{3-0};
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132
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133 let isAsCheapAsAMove = 1;
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134 }
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135
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136 //===----------------------------------------------------------------------===//
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137 // Register instruction: <|opcode|fffd|dddd|ffff|>
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138 // opcode = 4 bits.
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139 // f = secondary opcode = 7 bits
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140 // d = destination = 5 bits
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141 // (Accepts all registers)
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142 //===----------------------------------------------------------------------===//
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143 class FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr,
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144 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
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145 {
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146 bits<5> d;
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147
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148 let Inst{15-12} = opcode;
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149 let Inst{11-9} = f{6-4};
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150 let Inst{8-4} = d;
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151 let Inst{3-0} = f{3-0};
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152 }
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153
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154 //===----------------------------------------------------------------------===//
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155 // [STD/LDD] P+q, Rr special encoding: <|10q0|qqtr|rrrr|pqqq>
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156 // t = type (1 for STD, 0 for LDD)
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157 // q = displacement (6 bits)
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158 // r = register (5 bits)
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159 // p = pointer register (1 bit) [1 for Y, 0 for Z]
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160 //===----------------------------------------------------------------------===//
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161 class FSTDLDD<bit type, dag outs, dag ins, string asmstr, list<dag> pattern>
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162 : AVRInst16<outs, ins, asmstr, pattern>
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163 {
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164 bits<7> memri;
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165 bits<5> reg; // the GP register
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166
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167 let Inst{15-14} = 0b10;
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168 let Inst{13} = memri{5};
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169 let Inst{12} = 0;
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170
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171 let Inst{11-10} = memri{4-3};
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172 let Inst{9} = type;
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173 let Inst{8} = reg{4};
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174
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175 let Inst{7-4} = reg{3-0};
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176
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177 let Inst{3} = memri{6};
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178 let Inst{2-0} = memri{2-0};
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179 }
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180
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181 //===---------------------------------------------------------------------===//
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182 // An ST/LD instruction.
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183 // <|100i|00tr|rrrr|ppaa|>
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184 // t = type (1 for store, 0 for load)
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185 // a = regular/postinc/predec (reg = 0b00, postinc = 0b01, predec = 0b10)
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186 // p = pointer register
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187 // r = src/dst register
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188 //
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189 // Note that the bit labelled 'i' above does not follow a simple pattern,
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190 // so there exists a post encoder method to set it manually.
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191 //===---------------------------------------------------------------------===//
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192 class FSTLD<bit type, bits<2> mode, dag outs, dag ins,
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193 string asmstr, list<dag> pattern>
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194 : AVRInst16<outs, ins, asmstr, pattern>
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195 {
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196 bits<2> ptrreg;
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197 bits<5> reg;
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198
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199 let Inst{15-13} = 0b100;
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200 // This bit varies depending on the arguments and the mode.
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201 // We have a post encoder method to set this bit manually.
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202 let Inst{12} = 0;
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203
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204 let Inst{11-10} = 0b00;
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205 let Inst{9} = type;
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206 let Inst{8} = reg{4};
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207
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208 let Inst{7-4} = reg{3-0};
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209
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210 let Inst{3-2} = ptrreg{1-0};
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211 let Inst{1-0} = mode{1-0};
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212
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213 let PostEncoderMethod = "loadStorePostEncoder";
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214 }
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215
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216 //===---------------------------------------------------------------------===//
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217 // Special format for the LPM/ELPM instructions
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218 // [E]LPM Rd, Z[+]
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219 // <|1001|000d|dddd|01ep>
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220 // d = destination register
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221 // e = is elpm
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222 // p = is postincrement
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223 //===---------------------------------------------------------------------===//
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224 class FLPMX<bit e, bit p, dag outs, dag ins, string asmstr, list<dag> pattern>
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225 : AVRInst16<outs, ins, asmstr, pattern>
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226 {
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227 bits<5> reg;
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228
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229 let Inst{15-12} = 0b1001;
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230
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231 let Inst{11-9} = 0b000;
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232 let Inst{8} = reg{4};
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233
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234 let Inst{7-4} = reg{3-0};
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235
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236 let Inst{3-2} = 0b01;
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237 let Inst{1} = e;
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238 let Inst{0} = p;
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239 }
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240
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241 //===----------------------------------------------------------------------===//
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242 // MOVWRdRr special encoding: <|0000|0001|dddd|rrrr|>
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243 // d = destination = 4 bits
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244 // r = source = 4 bits
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245 // (Only accepts even registers)
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246 //===----------------------------------------------------------------------===//
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247 class FMOVWRdRr<dag outs, dag ins, string asmstr, list<dag> pattern>
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248 : AVRInst16<outs, ins, asmstr, pattern>
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249 {
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250 bits<5> d;
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251 bits<5> r;
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252
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253 let Inst{15-8} = 0b00000001;
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254 let Inst{7-4} = d{4-1};
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255 let Inst{3-0} = r{4-1};
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256 }
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257
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258 //===----------------------------------------------------------------------===//
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259 // MULSrr special encoding: <|0000|0010|dddd|rrrr|>
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260 // d = multiplicand = 4 bits
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261 // r = multiplier = 4 bits
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262 // (Only accepts r16-r31)
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263 //===----------------------------------------------------------------------===//
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264 class FMUL2RdRr<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
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265 : AVRInst16<outs, ins, asmstr, pattern>
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266 {
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267 bits<5> rd; // accept 5 bits but only encode the lower 4
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268 bits<5> rr; // accept 5 bits but only encode the lower 4
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269
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270 let Inst{15-9} = 0b0000001;
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271 let Inst{8} = f;
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272 let Inst{7-4} = rd{3-0};
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273 let Inst{3-0} = rr{3-0};
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274 }
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275
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276 // Special encoding for the FMUL family of instructions.
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277 //
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278 // <0000|0011|fddd|frrr|>
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279 //
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280 // ff = 0b01 for FMUL
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281 // 0b10 for FMULS
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282 // 0b11 for FMULSU
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283 //
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284 // ddd = destination register
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285 // rrr = source register
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286 class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern>
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287 : AVRInst16<outs, ins, asmstr, pattern>
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288 {
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289 bits<3> rd;
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290 bits<3> rr;
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291
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292 let Inst{15-8} = 0b00000011;
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293 let Inst{7} = f{1};
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294 let Inst{6-4} = rd;
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295 let Inst{3} = f{0};
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296 let Inst{2-0} = rr;
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297 }
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298
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299
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300 //===----------------------------------------------------------------------===//
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301 // Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|>
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302 // f = secondary opcode = 1 bit
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303 // k = constant data = 6 bits
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304 // d = destination = 4 bits
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305 // (Only accepts r25:24 r27:26 r29:28 r31:30)
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306 //===----------------------------------------------------------------------===//
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307 class FWRdK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
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308 : AVRInst16<outs, ins, asmstr, pattern>
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309 {
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310 bits<5> dst; // accept 5 bits but only encode bits 1 and 2
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311 bits<6> k;
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312
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313 let Inst{15-9} = 0b1001011;
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314 let Inst{8} = f;
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315 let Inst{7-6} = k{5-4};
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316 let Inst{5-4} = dst{2-1};
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317 let Inst{3-0} = k{3-0};
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318 }
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319
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320 //===----------------------------------------------------------------------===//
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321 // In I/O instruction: <|1011|0AAd|dddd|AAAA|>
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322 // A = I/O location address = 6 bits
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323 // d = destination = 5 bits
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324 // (Accepts all registers)
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325 //===----------------------------------------------------------------------===//
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326 class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern>
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327 : AVRInst16<outs, ins, asmstr, pattern>
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328 {
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329 bits<5> d;
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330 bits<6> A;
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331
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332 let Inst{15-11} = 0b10110;
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333 let Inst{10-9} = A{5-4};
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334 let Inst{8-4} = d;
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335 let Inst{3-0} = A{3-0};
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336 }
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337
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338 //===----------------------------------------------------------------------===//
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339 // Out I/O instruction: <|1011|1AAr|rrrr|AAAA|>
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340 // A = I/O location address = 6 bits
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341 // d = destination = 5 bits
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342 // (Accepts all registers)
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343 //===----------------------------------------------------------------------===//
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344 class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern>
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345 : AVRInst16<outs, ins, asmstr, pattern>
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346 {
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347 bits<6> A;
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348 bits<5> r;
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349
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350 let Inst{15-11} = 0b10111;
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351 let Inst{10-9} = A{5-4};
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352 let Inst{8-4} = r;
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353 let Inst{3-0} = A{3-0};
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354 }
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355
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356 //===----------------------------------------------------------------------===//
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357 // I/O bit instruction.
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358 // <|1001|10tt|AAAA|Abbb>
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359 // t = type (1 for SBI, 0 for CBI)
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360 // A = I/O location address (5 bits)
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361 // b = bit number
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362 //===----------------------------------------------------------------------===//
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363 class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
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364 : AVRInst16<outs, ins, asmstr, pattern>
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365 {
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366 bits<5> A;
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367 bits<3> b;
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368
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369 let Inst{15-12} = 0b1001;
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370
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371 let Inst{11-10} = 0b10;
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372 let Inst{9-8} = t;
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373
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374 let Inst{7-4} = A{4-1};
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375
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376 let Inst{3} = A{0};
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377 let Inst{2-0} = b{2-0};
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378 }
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379
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380 //===----------------------------------------------------------------------===//
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381 // BST/BLD instruction.
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382 // <|1111|1ttd|dddd|0bbb>
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383 // t = type (1 for BST, 0 for BLD)
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384 // d = destination register
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385 // b = bit
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386 //===----------------------------------------------------------------------===//
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387 class FRdB<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
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388 : AVRInst16<outs, ins, asmstr, pattern>
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389 {
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390 bits<5> rd;
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391 bits<3> b;
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392
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393 let Inst{15-12} = 0b1111;
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394
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395 let Inst{11} = 0b1;
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396 let Inst{10-9} = t;
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397 let Inst{8} = rd{4};
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398
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399 let Inst{7-4} = rd{3-0};
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400
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401 let Inst{3} = 0;
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402 let Inst{2-0} = b;
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403 }
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404
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405 // Special encoding for the `DES K` instruction.
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406 //
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407 // <|1001|0100|KKKK|1011>
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408 //
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409 // KKKK = 4 bit immediate
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410 class FDES<dag outs, dag ins, string asmstr, list<dag> pattern>
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411 : AVRInst16<outs, ins, asmstr, pattern>
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412 {
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413 bits<4> k;
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414
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415 let Inst{15-12} = 0b1001;
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416
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417 let Inst{11-8} = 0b0100;
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418
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419 let Inst{7-4} = k;
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420
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421 let Inst{3-0} = 0b1011;
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422 }
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423
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424 //===----------------------------------------------------------------------===//
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425 // Conditional Branching instructions: <|1111|0fkk|kkkk|ksss|>
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426 // f = secondary opcode = 1 bit
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427 // k = constant address = 7 bits
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428 // s = bit in status register = 3 bits
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429 //===----------------------------------------------------------------------===//
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430 class FBRsk<bit f, bits<3> s, dag outs, dag ins, string asmstr, list<dag> pattern>
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431 : AVRInst16<outs, ins, asmstr, pattern>
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432 {
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433 bits<7> k;
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434
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435 let Inst{15-11} = 0b11110;
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436 let Inst{10} = f;
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437 let Inst{9-3} = k;
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438 let Inst{2-0} = s;
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439 }
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440
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441 //===----------------------------------------------------------------------===//
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442 // Special, opcode only instructions: <|opcode|>
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443 //===----------------------------------------------------------------------===//
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444
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445 class F16<bits<16> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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446 : AVRInst16<outs, ins, asmstr, pattern>
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447 {
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448 let Inst = opcode;
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449 }
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450
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451 class F32<bits<32> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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452 : AVRInst32<outs, ins, asmstr, pattern>
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453 {
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454 let Inst = opcode;
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455 }
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456
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457 //===----------------------------------------------------------------------===//
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458 // Branching instructions with immediate12: <|110f|kkkk|kkkk|kkkk|>
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459 // f = secondary opcode = 1 bit
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460 // k = constant address = 12 bits
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461 //===----------------------------------------------------------------------===//
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462 class FBRk<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
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463 : AVRInst16<outs, ins, asmstr, pattern>
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464 {
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465 bits<12> k;
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466
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467 let Inst{15-13} = 0b110;
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468 let Inst{12} = f;
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469 let Inst{11-0} = k;
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470 }
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471
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|
472 //===----------------------------------------------------------------------===//
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473 // 32 bits branching instructions: <|1001|010k|kkkk|fffk|kkkk|kkkk|kkkk|kkkk|>
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474 // f = secondary opcode = 3 bits
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475 // k = constant address = 22 bits
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476 //===----------------------------------------------------------------------===//
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477 class F32BRk<bits<3> f, dag outs, dag ins, string asmstr, list<dag> pattern>
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478 : AVRInst32<outs, ins, asmstr, pattern>
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|
|
479 {
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480 bits<22> k;
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481
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482 let Inst{31-25} = 0b1001010;
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483 let Inst{24-20} = k{21-17};
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484 let Inst{19-17} = f;
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485 let Inst{16-0} = k{16-0};
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|
|
486 }
|
|
|
487
|
|
|
488 //===----------------------------------------------------------------------===//
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|
|
489 // 32 bits direct mem instructions: <|1001|00fd|dddd|0000|kkkk|kkkk|kkkk|kkkk|>
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|
490 // f = secondary opcode = 1 bit
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491 // d = destination = 5 bits
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|
492 // k = constant address = 16 bits
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|
493 // (Accepts all registers)
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|
|
494 //===----------------------------------------------------------------------===//
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|
|
495 class F32DM<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
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496 : AVRInst32<outs, ins, asmstr, pattern>
|
|
|
497 {
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|
|
498 bits<5> rd;
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|
|
499 bits<16> k;
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|
|
500
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|
|
501 let Inst{31-28} = 0b1001;
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|
|
502
|
|
|
503 let Inst{27-26} = 0b00;
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|
|
504 let Inst{25} = f;
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|
|
505 let Inst{24} = rd{4};
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|
|
506
|
|
|
507 let Inst{23-20} = rd{3-0};
|
|
|
508
|
|
|
509 let Inst{19-16} = 0b0000;
|
|
|
510
|
|
|
511 let Inst{15-0} = k;
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|
|
512 }
|
|
|
513
|
|
|
514 // <|1001|0100|bfff|1000>
|
|
|
515 class FS<bit b, dag outs, dag ins, string asmstr, list<dag> pattern>
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|
|
516 : AVRInst16<outs, ins, asmstr, pattern>
|
|
|
517 {
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|
|
518 bits<3> s;
|
|
|
519
|
|
|
520 let Inst{15-12} = 0b1001;
|
|
|
521
|
|
|
522 let Inst{11-8} = 0b0100;
|
|
|
523
|
|
|
524 let Inst{7} = b;
|
|
|
525 let Inst{6-4} = s;
|
|
|
526
|
|
|
527 let Inst{3-0} = 0b1000;
|
|
|
528 }
|
|
|
529
|
|
|
530 // Set/clr bit in status flag instructions/
|
|
|
531 // <BRBS|BRBC> s, k
|
|
|
532 // ---------------------
|
|
|
533 // <|1111|0fkk|kkkk|ksss>
|
|
|
534 class FSK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
535 : AVRInst16<outs, ins, asmstr, pattern>
|
|
|
536 {
|
|
|
537 bits<7> k;
|
|
|
538 bits<3> s;
|
|
|
539
|
|
|
540 let Inst{15-12} = 0b1111;
|
|
|
541
|
|
|
542 let Inst{11} = 0;
|
|
|
543 let Inst{10} = f;
|
|
|
544 let Inst{9-8} = k{6-5};
|
|
|
545
|
|
|
546 let Inst{7-4} = k{4-1};
|
|
|
547
|
|
|
548 let Inst{3} = k{0};
|
|
|
549 let Inst{2-0} = s;
|
|
|
550 }
|
|
|
551
|
|
|
552 class ExtensionPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
553 : Pseudo<outs, ins, asmstr, pattern>
|
|
|
554 {
|
|
|
555 let Defs = [SREG];
|
|
|
556 }
|
|
|
557
|
|
|
558 class StorePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
559 : Pseudo<outs, ins, asmstr, pattern>
|
|
|
560 {
|
|
|
561 let Defs = [SP];
|
|
|
562 }
|
|
|
563
|
|
|
564 class SelectPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
565 : Pseudo<outs, ins, asmstr, pattern>
|
|
|
566 {
|
|
|
567 let usesCustomInserter = 1;
|
|
|
568
|
|
|
569 let Uses = [SREG];
|
|
|
570 }
|
|
|
571
|
|
|
572 class ShiftPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
573 : Pseudo<outs, ins, asmstr, pattern>
|
|
|
574 {
|
|
|
575 let usesCustomInserter = 1;
|
|
|
576
|
|
|
577 let Defs = [SREG];
|
|
|
578 }
|
|
|
579
|
