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120
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1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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2 ; RUN: -check-prefixes=ALL,M2,M2-M3
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3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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4 ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
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5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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6 ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
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8 ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
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10 ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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12 ; RUN: -check-prefixes=ALL,SEL,SEL-32
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13 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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14 ; RUN: -check-prefixes=ALL,M3,M2-M3
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15 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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16 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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17 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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18 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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19 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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20 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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21 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
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22 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
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24 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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25 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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26 ; RUN: -check-prefixes=ALL,SEL,SEL-64
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27 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
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28 ; RUN: -check-prefixes=ALL,MM32R3
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29 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
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30 ; RUN: -check-prefixes=ALL,MMR6,MM32R6
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31
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32 define signext i1 @tst_select_i1_i1(i1 signext %s,
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33 i1 signext %x, i1 signext %y) {
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34 entry:
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35 ; ALL-LABEL: tst_select_i1_i1:
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36
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37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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38 ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
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39 ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
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40 ; M2-M3: nop
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41 ; M2-M3: move $5, $6
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42 ; M2-M3: [[BB0]]:
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43 ; M2-M3: jr $ra
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44 ; M2-M3: move $2, $5
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45
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46 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
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47 ; CMOV: movn $6, $5, $[[T0]]
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48 ; CMOV: move $2, $6
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49
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50 ; SEL: andi $[[T0:[0-9]+]], $4, 1
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51 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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52 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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53 ; SEL: or $2, $[[T2]], $[[T1]]
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54
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55 ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
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56 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
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57 ; MM32R3: move $2, $[[T1]]
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58
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59 ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
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60 ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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61 ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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62 ; MMR6: or $2, $[[T2]], $[[T1]]
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63
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64 %r = select i1 %s, i1 %x, i1 %y
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65 ret i1 %r
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66 }
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67
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68 define signext i8 @tst_select_i1_i8(i1 signext %s,
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69 i8 signext %x, i8 signext %y) {
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70 entry:
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71 ; ALL-LABEL: tst_select_i1_i8:
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72
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73 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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74 ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
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75 ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
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76 ; M2-M3: nop
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77 ; M2-M3: move $5, $6
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78 ; M2-M3: [[BB0]]:
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79 ; M2-M3: jr $ra
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80 ; M2-M3: move $2, $5
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81
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82 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
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83 ; CMOV: movn $6, $5, $[[T0]]
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84 ; CMOV: move $2, $6
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85
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86 ; SEL: andi $[[T0:[0-9]+]], $4, 1
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87 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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88 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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89 ; SEL: or $2, $[[T2]], $[[T1]]
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90
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91 ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
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92 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
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93 ; MM32R3: move $2, $[[T1]]
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94
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95 ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
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96 ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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97 ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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98 ; MMR6: or $2, $[[T2]], $[[T1]]
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99
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100 %r = select i1 %s, i8 %x, i8 %y
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101 ret i8 %r
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102 }
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103
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104 define signext i32 @tst_select_i1_i32(i1 signext %s,
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105 i32 signext %x, i32 signext %y) {
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106 entry:
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107 ; ALL-LABEL: tst_select_i1_i32:
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108
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109 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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110 ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
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111 ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
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112 ; M2-M3: nop
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113 ; M2-M3: move $5, $6
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114 ; M2-M3: [[BB0]]:
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115 ; M2-M3: jr $ra
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116 ; M2-M3: move $2, $5
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117
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118 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
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119 ; CMOV: movn $6, $5, $[[T0]]
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120 ; CMOV: move $2, $6
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121
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122 ; SEL: andi $[[T0:[0-9]+]], $4, 1
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123 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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124 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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125 ; SEL: or $2, $[[T2]], $[[T1]]
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126
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127 ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
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128 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
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129 ; MM32R3: move $2, $[[T1]]
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130
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131 ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
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132 ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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133 ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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134 ; MMR6: or $2, $[[T2]], $[[T1]]
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135
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136 %r = select i1 %s, i32 %x, i32 %y
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137 ret i32 %r
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138 }
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139
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140 define signext i64 @tst_select_i1_i64(i1 signext %s,
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141 i64 signext %x, i64 signext %y) {
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142 entry:
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143 ; ALL-LABEL: tst_select_i1_i64:
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144
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145 ; M2: andi $[[T0:[0-9]+]], $4, 1
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146 ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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147 ; M2: nop
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148 ; M2: lw $[[T1:[0-9]+]], 16($sp)
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149 ; M2: $[[BB0]]:
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150 ; FIXME: This branch is redundant
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151 ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
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152 ; M2: nop
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153 ; M2: lw $[[T2:[0-9]+]], 20($sp)
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154 ; M2: $[[BB1]]:
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155 ; M2: move $2, $[[T1]]
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156 ; M2: jr $ra
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157 ; M2: move $3, $[[T2]]
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158
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159 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
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160 ; CMOV-32: lw $2, 16($sp)
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161 ; CMOV-32: movn $2, $6, $[[T0]]
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162 ; CMOV-32: lw $3, 20($sp)
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163 ; CMOV-32: movn $3, $7, $[[T0]]
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164
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165 ; SEL-32: andi $[[T0:[0-9]+]], $4, 1
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166 ; SEL-32: lw $[[T1:[0-9]+]], 16($sp)
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167 ; SEL-32: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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168 ; SEL-32: selnez $[[T3:[0-9]+]], $6, $[[T0]]
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169 ; SEL-32: or $2, $[[T3]], $[[T2]]
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170 ; SEL-32: lw $[[T4:[0-9]+]], 20($sp)
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171 ; SEL-32: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
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172 ; SEL-32: selnez $[[T6:[0-9]+]], $7, $[[T0]]
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173 ; SEL-32: or $3, $[[T6]], $[[T5]]
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174
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175 ; M3: andi $[[T0:[0-9]+]], $4, 1
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176 ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
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177 ; M3: nop
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178 ; M3: move $5, $6
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179 ; M3: [[BB0]]:
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180 ; M3: jr $ra
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181 ; M3: move $2, $5
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182
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183 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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184 ; CMOV-64: movn $6, $5, $[[T0]]
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185 ; CMOV-64: move $2, $6
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186
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187 ; SEL-64: andi $[[T0:[0-9]+]], $4, 1
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188 ; FIXME: This shift is redundant
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189 ; SEL-64: sll $[[T0]], $[[T0]], 0
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190 ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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191 ; SEL-64: selnez $[[T0]], $5, $[[T0]]
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192 ; SEL-64: or $2, $[[T0]], $[[T1]]
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193
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194 ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
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195 ; MM32R3: lw $2, 16($sp)
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196 ; MM32R3: movn $2, $6, $[[T0]]
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197 ; MM32R3: lw $3, 20($sp)
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198 ; MM32R3: movn $3, $7, $[[T0]]
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199
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200 ; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1
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201 ; MM32R6: lw $[[T2:[0-9]+]], 16($sp)
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202 ; MM32R6: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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203 ; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]]
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204 ; MM32R6: or $2, $[[T1]], $[[T3]]
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205 ; MM32R6: lw $[[T4:[0-9]+]], 20($sp)
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206 ; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
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207 ; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
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208 ; MM32R6: or $3, $[[T6]], $[[T5]]
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209
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210 %r = select i1 %s, i64 %x, i64 %y
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211 ret i64 %r
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212 }
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213
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214 define i8* @tst_select_word_cst(i8* %a, i8* %b) {
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215 ; ALL-LABEL: tst_select_word_cst:
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216
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217 ; M2: addiu $[[T0:[0-9]+]], $zero, -1
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218 ; M2: xor $[[T1:[0-9]+]], $5, $[[T0]]
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219 ; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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220 ; M2: bnez $[[T2]], [[BB0:\$BB[0-9_]+]]
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221 ; M2: addiu $2, $zero, 0
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222 ; M2: move $2, $4
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223 ; M2: [[BB0]]:
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224 ; M2: jr $ra
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225
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226 ; M3: daddiu $[[T0:[0-9]+]], $zero, -1
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227 ; M3: xor $[[T1:[0-9]+]], $5, $[[T0]]
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228 ; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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229 ; M3: bnez $[[T2]], [[BB0:\.LBB[0-9_]+]]
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230 ; M3: daddiu $2, $zero, 0
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231 ; M3: move $2, $4
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232 ; M3: [[BB0]]:
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233 ; M3: jr $ra
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234
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235 ; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1
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236 ; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
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237 ; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]]
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238 ; CMOV-32: jr $ra
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239 ; CMOV-32: move $2, $[[T2]]
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240
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241 ; SEL-32: addiu $[[T0:[0-9]+]], $zero, -1
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242 ; SEL-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
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243 ; SEL-32: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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244 ; SEL-32: jr $ra
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245 ; SEL-32: seleqz $2, $4, $[[T2]]
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246
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247 ; CMOV-64: daddiu $[[T0:[0-9]+]], $zero, -1
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248 ; CMOV-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
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249 ; CMOV-64: movn $[[T2:[0-9]+]], $zero, $[[T1]]
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250 ; CMOV-64: move $2, $[[T2]]
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251
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252 ; SEL-64: daddiu $[[T0:[0-9]+]], $zero, -1
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253 ; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
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254 ; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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255 ; FIXME: This shift is redundant.
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256 ; SEL-64: sll $[[T2]], $[[T2]], 0
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257 ; SEL-64: seleqz $2, $4, $[[T2]]
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258
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259 ; MM32R3: li16 $[[T0:[0-9]+]], -1
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260 ; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]]
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261 ; MM32R3: li16 $[[T2:[0-9]+]], 0
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262 ; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]]
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263 ; MM32R3: move $2, $[[T3]]
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264
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265 ; MM32R6: li16 $[[T0:[0-9]+]], -1
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266 ; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]]
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267 ; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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268 ; MM32R6: seleqz $2, $4, $[[T2]]
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269
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270 %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
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271 %r = select i1 %cmp, i8* %a, i8* null
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272 ret i8* %r
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273 }
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