annotate test/CodeGen/AMDGPU/extract_vector_elt-f16.ll @ 146:3fc4d5c3e21e

set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 3a76565eade5
children c2174574ed3a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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2 ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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3
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4 ; GCN-LABEL: {{^}}extract_vector_elt_v2f16:
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5 ; GCN: s_load_dword [[VEC:s[0-9]+]]
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6 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
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7 ; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]]
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8 ; GCN-DAG: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
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9 ; GCN-DAG: buffer_store_short [[VELT0]]
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10 ; GCN-DAG: buffer_store_short [[VELT1]]
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11 define amdgpu_kernel void @extract_vector_elt_v2f16(half addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr) #0 {
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12 %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
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13 %p0 = extractelement <2 x half> %vec, i32 0
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14 %p1 = extractelement <2 x half> %vec, i32 1
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15 %out1 = getelementptr half, half addrspace(1)* %out, i32 10
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16 store half %p1, half addrspace(1)* %out, align 2
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17 store half %p0, half addrspace(1)* %out1, align 2
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18 ret void
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19 }
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20
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21 ; GCN-LABEL: {{^}}extract_vector_elt_v2f16_dynamic_sgpr:
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22 ; GCN: s_load_dword [[IDX:s[0-9]+]]
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23 ; GCN: s_load_dword [[VEC:s[0-9]+]]
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24 ; GCN: s_lshl_b32 [[IDX_SCALED:s[0-9]+]], [[IDX]], 16
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25 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]]
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26 ; GCN: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
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27 ; GCN: buffer_store_short [[VELT1]]
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28 ; GCN: ScratchSize: 0
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29 define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_sgpr(half addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr, i32 %idx) #0 {
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30 %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
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31 %elt = extractelement <2 x half> %vec, i32 %idx
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32 store half %elt, half addrspace(1)* %out, align 2
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33 ret void
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34 }
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35
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36 ; GCN-LABEL: {{^}}extract_vector_elt_v2f16_dynamic_vgpr:
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37 ; GCN-DAG: s_load_dword [[VEC:s[0-9]+]]
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38 ; GCN-DAG: {{flat|buffer}}_load_dword [[IDX:v[0-9]+]]
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39 ; GCN: v_lshlrev_b32_e32 [[IDX_SCALED:v[0-9]+]], 16, [[IDX]]
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40
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41 ; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]]
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42 ; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]]
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43
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44
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45 ; SI: buffer_store_short [[ELT]]
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46 ; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[ELT]]
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47 ; GCN: ScratchSize: 0{{$}}
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48 define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_vgpr(half addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr, i32 addrspace(1)* %idx.ptr) #0 {
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49 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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50 %tid.ext = sext i32 %tid to i64
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51 %gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext
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52 %out.gep = getelementptr inbounds half, half addrspace(1)* %out, i64 %tid.ext
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53 %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
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54 %idx = load i32, i32 addrspace(1)* %gep
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55 %elt = extractelement <2 x half> %vec, i32 %idx
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56 store half %elt, half addrspace(1)* %out.gep, align 2
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57 ret void
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58 }
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59
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60 ; GCN-LABEL: {{^}}extract_vector_elt_v3f16:
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61 ; GCN: buffer_load_ushort
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62 ; GCN: buffer_store_short
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63 ; GCN: buffer_store_short
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64 define amdgpu_kernel void @extract_vector_elt_v3f16(half addrspace(1)* %out, <3 x half> %foo) #0 {
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65 %p0 = extractelement <3 x half> %foo, i32 0
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66 %p1 = extractelement <3 x half> %foo, i32 2
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67 %out1 = getelementptr half, half addrspace(1)* %out, i32 1
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68 store half %p1, half addrspace(1)* %out, align 2
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69 store half %p0, half addrspace(1)* %out1, align 2
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70 ret void
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71 }
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72
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73 ; GCN-LABEL: {{^}}extract_vector_elt_v4f16:
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74 ; GCN: buffer_load_ushort
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75 ; GCN: buffer_load_ushort
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76 ; GCN: buffer_store_short
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77 ; GCN: buffer_store_short
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78 define amdgpu_kernel void @extract_vector_elt_v4f16(half addrspace(1)* %out, <4 x half> %foo) #0 {
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79 %p0 = extractelement <4 x half> %foo, i32 0
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80 %p1 = extractelement <4 x half> %foo, i32 2
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81 %out1 = getelementptr half, half addrspace(1)* %out, i32 10
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82 store half %p1, half addrspace(1)* %out, align 2
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83 store half %p0, half addrspace(1)* %out1, align 2
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84 ret void
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85 }
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86
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87 ; GCN-LABEL: {{^}}dynamic_extract_vector_elt_v3f16:
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88 ; GCN: buffer_load_ushort
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89 ; GCN: buffer_load_ushort
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90 ; GCN: buffer_load_ushort
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91
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92 ; GCN: buffer_store_short
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93 ; GCN: buffer_store_short
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94 ; GCN: buffer_store_short
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95
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96 ; GCN: buffer_load_ushort
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97 ; GCN: buffer_store_short
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98 define amdgpu_kernel void @dynamic_extract_vector_elt_v3f16(half addrspace(1)* %out, <3 x half> %foo, i32 %idx) #0 {
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99 %p0 = extractelement <3 x half> %foo, i32 %idx
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100 %out1 = getelementptr half, half addrspace(1)* %out, i32 1
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101 store half %p0, half addrspace(1)* %out
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102 ret void
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103 }
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104
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105 ; GCN-LABEL: {{^}}dynamic_extract_vector_elt_v4f16:
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106 ; GCN: buffer_load_ushort
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107 ; GCN: buffer_load_ushort
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108 ; GCN: buffer_load_ushort
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109 ; GCN: buffer_load_ushort
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110
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111 ; GCN: buffer_store_short
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112 ; GCN: buffer_store_short
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113 ; GCN: buffer_store_short
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114 ; GCN: buffer_store_short
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115
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116 ; GCN: buffer_load_ushort
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117 ; GCN: buffer_store_short
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118 define amdgpu_kernel void @dynamic_extract_vector_elt_v4f16(half addrspace(1)* %out, <4 x half> %foo, i32 %idx) #0 {
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119 %p0 = extractelement <4 x half> %foo, i32 %idx
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120 %out1 = getelementptr half, half addrspace(1)* %out, i32 1
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121 store half %p0, half addrspace(1)* %out
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122 ret void
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123 }
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124
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125 declare i32 @llvm.amdgcn.workitem.id.x() #1
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126
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127 attributes #0 = { nounwind }
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128 attributes #1 = { nounwind readnone }