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annotate test/CodeGen/AMDGPU/fneg-fabs.f64.ll @ 146:3fc4d5c3e21e

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set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 803732b1fca8
children c2174574ed3a
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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4 ; FIXME: Check something here. Currently it seems fabs + fneg aren't
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5 ; into 2 modifiers, although theoretically that should work.
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7 ; GCN-LABEL: {{^}}fneg_fabs_fadd_f64:
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8 ; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|
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9 define amdgpu_kernel void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) {
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10 %fabs = call double @llvm.fabs.f64(double %x)
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11 %fsub = fsub double -0.000000e+00, %fabs
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12 %fadd = fadd double %y, %fsub
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13 store double %fadd, double addrspace(1)* %out, align 8
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14 ret void
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15 }
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16
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17 define amdgpu_kernel void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %xptr, double addrspace(1)* %yptr) {
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18 %x = load double, double addrspace(1)* %xptr, align 8
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19 %y = load double, double addrspace(1)* %xptr, align 8
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20 %fabs = call double @llvm.fabs.f64(double %x)
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21 %fsub = fsub double -0.000000e+00, %fabs
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22 %fadd = fadd double %y, %fsub
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23 store double %fadd, double addrspace(1)* %out, align 8
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24 ret void
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25 }
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26
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27 ; GCN-LABEL: {{^}}fneg_fabs_fmul_f64:
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28 ; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|
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29 define amdgpu_kernel void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) {
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30 %fabs = call double @llvm.fabs.f64(double %x)
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31 %fsub = fsub double -0.000000e+00, %fabs
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32 %fmul = fmul double %y, %fsub
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33 store double %fmul, double addrspace(1)* %out, align 8
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34 ret void
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35 }
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37 ; GCN-LABEL: {{^}}fneg_fabs_free_f64:
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38 define amdgpu_kernel void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) {
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39 %bc = bitcast i64 %in to double
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40 %fabs = call double @llvm.fabs.f64(double %bc)
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41 %fsub = fsub double -0.000000e+00, %fabs
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42 store double %fsub, double addrspace(1)* %out
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43 ret void
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44 }
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45
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46 ; GCN-LABEL: {{^}}fneg_fabs_fn_free_f64:
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47 ; GCN: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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48 ; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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49 define amdgpu_kernel void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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50 %bc = bitcast i64 %in to double
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51 %fabs = call double @fabs(double %bc)
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52 %fsub = fsub double -0.000000e+00, %fabs
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53 store double %fsub, double addrspace(1)* %out
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54 ret void
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55 }
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56
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57 ; GCN-LABEL: {{^}}fneg_fabs_f64:
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58 ; GCN-DAG: s_load_dwordx2
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59 ; GCN-DAG: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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60 ; SI-DAG: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xb
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61 ; VI-DAG: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x2c
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62 ; GCN-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]]
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63 ; GCN-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
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64 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}}
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65 define amdgpu_kernel void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
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66 %fabs = call double @llvm.fabs.f64(double %in)
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67 %fsub = fsub double -0.000000e+00, %fabs
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68 store double %fsub, double addrspace(1)* %out, align 8
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69 ret void
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70 }
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71
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72 ; GCN-LABEL: {{^}}fneg_fabs_v2f64:
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73 ; GCN: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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74 ; GCN-NOT: 0x80000000
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75 ; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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76 ; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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77 define amdgpu_kernel void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
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78 %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
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79 %fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs
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80 store <2 x double> %fsub, <2 x double> addrspace(1)* %out
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81 ret void
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82 }
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83
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84 ; GCN-LABEL: {{^}}fneg_fabs_v4f64:
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85 ; GCN: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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86 ; GCN-NOT: 0x80000000
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87 ; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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88 ; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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89 ; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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90 ; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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91 define amdgpu_kernel void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
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92 %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
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93 %fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs
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94 store <4 x double> %fsub, <4 x double> addrspace(1)* %out
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95 ret void
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96 }
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97
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98 declare double @fabs(double) readnone
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99 declare double @llvm.fabs.f64(double) readnone
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100 declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
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101 declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone