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134
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
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120
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4
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5 ; GCN-LABEL: {{^}}fpext_f16_to_f32
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6 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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7 ; GCN: v_cvt_f32_f16_e32 v[[R_F32:[0-9]+]], v[[A_F16]]
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8 ; GCN: buffer_store_dword v[[R_F32]]
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9 ; GCN: s_endpgm
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121
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10 define amdgpu_kernel void @fpext_f16_to_f32(
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120
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11 float addrspace(1)* %r,
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121
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12 half addrspace(1)* %a) #0 {
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120
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13 entry:
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14 %a.val = load half, half addrspace(1)* %a
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15 %r.val = fpext half %a.val to float
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16 store float %r.val, float addrspace(1)* %r
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17 ret void
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18 }
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19
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20 ; GCN-LABEL: {{^}}fpext_f16_to_f64
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21 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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22 ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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23 ; GCN: v_cvt_f64_f32_e32 v{{\[}}[[R_F64_0:[0-9]+]]:[[R_F64_1:[0-9]+]]{{\]}}, v[[A_F32]]
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24 ; GCN: buffer_store_dwordx2 v{{\[}}[[R_F64_0]]:[[R_F64_1]]{{\]}}
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25 ; GCN: s_endpgm
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121
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26 define amdgpu_kernel void @fpext_f16_to_f64(
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120
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27 double addrspace(1)* %r,
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121
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28 half addrspace(1)* %a) #0 {
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120
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29 entry:
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30 %a.val = load half, half addrspace(1)* %a
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31 %r.val = fpext half %a.val to double
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32 store double %r.val, double addrspace(1)* %r
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33 ret void
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34 }
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35
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36 ; GCN-LABEL: {{^}}fpext_v2f16_to_v2f32
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37 ; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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121
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38 ; GCN-DAG: v_cvt_f32_f16_e32 v[[R_F32_0:[0-9]+]], v[[A_V2_F16]]
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120
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39 ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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121
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40 ; SI: v_cvt_f32_f16_e32 v[[R_F32_1:[0-9]+]], v[[A_F16_1]]
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41 ; GFX89: v_cvt_f32_f16_sdwa v[[R_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
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120
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42 ; GCN: buffer_store_dwordx2 v{{\[}}[[R_F32_0]]:[[R_F32_1]]{{\]}}
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43 ; GCN: s_endpgm
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121
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44
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45 define amdgpu_kernel void @fpext_v2f16_to_v2f32(
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120
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46 <2 x float> addrspace(1)* %r,
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121
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47 <2 x half> addrspace(1)* %a) #0 {
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120
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48 entry:
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49 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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50 %r.val = fpext <2 x half> %a.val to <2 x float>
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51 store <2 x float> %r.val, <2 x float> addrspace(1)* %r
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52 ret void
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53 }
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54
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55 ; GCN-LABEL: {{^}}fpext_v2f16_to_v2f64
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121
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56 ; GCN: buffer_load_dword
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57 ; SI-DAG: v_lshrrev_b32_e32
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58 ; SI-DAG: v_cvt_f32_f16_e32
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59 ; GFX89: v_cvt_f32_f16_sdwa
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60 ; GCN: v_cvt_f32_f16_e32
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61
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62 ; GCN: v_cvt_f64_f32_e32
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63 ; GCN: v_cvt_f64_f32_e32
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64 ; GCN: buffer_store_dwordx4
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120
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65 ; GCN: s_endpgm
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121
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66
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67 define amdgpu_kernel void @fpext_v2f16_to_v2f64(
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120
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68 <2 x double> addrspace(1)* %r,
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69 <2 x half> addrspace(1)* %a) {
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70 entry:
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71 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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72 %r.val = fpext <2 x half> %a.val to <2 x double>
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73 store <2 x double> %r.val, <2 x double> addrspace(1)* %r
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74 ret void
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75 }
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121
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76
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77 ; GCN-LABEL: {{^}}s_fneg_fpext_f16_to_f32:
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78 ; GCN: v_cvt_f32_f16_e32 v{{[0-9]+}}, s{{[0-9]+}}
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79 define amdgpu_kernel void @s_fneg_fpext_f16_to_f32(float addrspace(1)* %r, i32 %a) {
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80 entry:
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81 %a.trunc = trunc i32 %a to i16
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82 %a.val = bitcast i16 %a.trunc to half
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83 %r.val = fpext half %a.val to float
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84 store float %r.val, float addrspace(1)* %r
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85 ret void
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86 }
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87
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88 ; GCN-LABEL: {{^}}fneg_fpext_f16_to_f32:
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89 ; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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90 ; GCN: v_cvt_f32_f16_e64 v{{[0-9]+}}, -[[A]]
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91 define amdgpu_kernel void @fneg_fpext_f16_to_f32(
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92 float addrspace(1)* %r,
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93 half addrspace(1)* %a) {
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94 entry:
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95 %a.val = load half, half addrspace(1)* %a
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96 %a.neg = fsub half -0.0, %a.val
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97 %r.val = fpext half %a.neg to float
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98 store float %r.val, float addrspace(1)* %r
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99 ret void
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100 }
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101
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102 ; GCN-LABEL: {{^}}fabs_fpext_f16_to_f32:
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103 ; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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104 ; GCN: v_cvt_f32_f16_e64 v{{[0-9]+}}, |[[A]]|
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105 define amdgpu_kernel void @fabs_fpext_f16_to_f32(
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106 float addrspace(1)* %r,
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107 half addrspace(1)* %a) {
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108 entry:
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109 %a.val = load half, half addrspace(1)* %a
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110 %a.fabs = call half @llvm.fabs.f16(half %a.val)
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111 %r.val = fpext half %a.fabs to float
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112 store float %r.val, float addrspace(1)* %r
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113 ret void
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114 }
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115
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116 ; GCN-LABEL: {{^}}fneg_fabs_fpext_f16_to_f32:
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117 ; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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118 ; GCN: v_cvt_f32_f16_e64 v{{[0-9]+}}, -|[[A]]|
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119 define amdgpu_kernel void @fneg_fabs_fpext_f16_to_f32(
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120 float addrspace(1)* %r,
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121 half addrspace(1)* %a) {
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122 entry:
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123 %a.val = load half, half addrspace(1)* %a
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124 %a.fabs = call half @llvm.fabs.f16(half %a.val)
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125 %a.fneg.fabs = fsub half -0.0, %a.fabs
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126 %r.val = fpext half %a.fneg.fabs to float
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127 store float %r.val, float addrspace(1)* %r
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128 ret void
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129 }
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130
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131 ; GCN-LABEL: {{^}}fneg_multi_use_fpext_f16_to_f32:
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132 ; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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133 ; GCN-DAG: v_xor_b32_e32 [[XOR:v[0-9]+]], 0x8000, [[A]]
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134
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135 ; FIXME: Using the source modifier here only wastes code size
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136 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], [[A]]
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137 ; GFX89-DAG: v_cvt_f32_f16_e64 [[CVT:v[0-9]+]], -[[A]]
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138
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139 ; GCN: store_dword [[CVT]]
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140 ; GCN: store_short [[XOR]]
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141 define amdgpu_kernel void @fneg_multi_use_fpext_f16_to_f32(
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142 float addrspace(1)* %r,
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143 half addrspace(1)* %a) {
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144 entry:
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145 %a.val = load half, half addrspace(1)* %a
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146 %a.neg = fsub half -0.0, %a.val
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147 %r.val = fpext half %a.neg to float
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148 store volatile float %r.val, float addrspace(1)* %r
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149 store volatile half %a.neg, half addrspace(1)* undef
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150 ret void
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151 }
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152
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153 ; GCN-LABEL: {{^}}fneg_multi_foldable_use_fpext_f16_to_f32:
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154 ; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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155 ; GCN-DAG: v_cvt_f32_f16_e64 [[CVTA_NEG:v[0-9]+]], -[[A]]
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156 ; SI-DAG: v_cvt_f32_f16_e32 [[CVTA:v[0-9]+]], [[A]]
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157 ; SI: v_mul_f32_e32 [[MUL_F32:v[0-9]+]], [[CVTA_NEG]], [[CVTA]]
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158 ; SI: v_cvt_f16_f32_e32 [[MUL:v[0-9]+]], [[MUL_F32]]
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159
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160 ; GFX89-DAG: v_cvt_f32_f16_e64 [[CVT_NEGA:v[0-9]+]], -[[A]]
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161 ; GFX89: v_mul_f16_e64 [[MUL:v[0-9]+]], -[[A]], [[A]]
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162
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163 ; GCN: buffer_store_dword [[CVTA_NEG]]
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164 ; GCN: buffer_store_short [[MUL]]
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165 define amdgpu_kernel void @fneg_multi_foldable_use_fpext_f16_to_f32(
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166 float addrspace(1)* %r,
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167 half addrspace(1)* %a) {
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168 entry:
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169 %a.val = load half, half addrspace(1)* %a
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170 %a.neg = fsub half -0.0, %a.val
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171 %r.val = fpext half %a.neg to float
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172 %mul = fmul half %a.neg, %a.val
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173 store volatile float %r.val, float addrspace(1)* %r
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174 store volatile half %mul, half addrspace(1)* undef
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175 ret void
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176 }
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177
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178 ; GCN-LABEL: {{^}}fabs_multi_use_fpext_f16_to_f32:
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179 ; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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180 ; GCN-DAG: v_and_b32_e32 [[XOR:v[0-9]+]], 0x7fff, [[A]]
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181
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182 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], [[A]]
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134
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183 ; GFX89-DAG: v_cvt_f32_f16_e64 [[CVT:v[0-9]+]], |[[A]]|
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121
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184
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185 ; GCN: store_dword [[CVT]]
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186 ; GCN: store_short [[XOR]]
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187 define amdgpu_kernel void @fabs_multi_use_fpext_f16_to_f32(
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188 float addrspace(1)* %r,
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189 half addrspace(1)* %a) {
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190 entry:
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191 %a.val = load half, half addrspace(1)* %a
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192 %a.fabs = call half @llvm.fabs.f16(half %a.val)
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193 %r.val = fpext half %a.fabs to float
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194 store volatile float %r.val, float addrspace(1)* %r
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195 store volatile half %a.fabs, half addrspace(1)* undef
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196 ret void
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197 }
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198
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199 ; GCN-LABEL: {{^}}fabs_multi_foldable_use_fpext_f16_to_f32:
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200 ; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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201 ; SI: v_cvt_f32_f16_e32 [[CVTA:v[0-9]+]], [[A]]
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202 ; SI: v_mul_f32_e64 [[MUL_F32:v[0-9]+]], |[[CVTA]]|, [[CVTA]]
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203 ; SI: v_cvt_f16_f32_e32 [[MUL:v[0-9]+]], [[MUL_F32]]
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204 ; SI: v_and_b32_e32 [[ABS_A:v[0-9]+]], 0x7fffffff, [[CVTA]]
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205
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206 ; GFX89-DAG: v_cvt_f32_f16_e64 [[ABS_A:v[0-9]+]], |[[A]]|
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207 ; GFX89: v_mul_f16_e64 [[MUL:v[0-9]+]], |[[A]]|, [[A]]
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208
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209 ; GCN: buffer_store_dword [[ABS_A]]
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210 ; GCN: buffer_store_short [[MUL]]
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211 define amdgpu_kernel void @fabs_multi_foldable_use_fpext_f16_to_f32(
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212 float addrspace(1)* %r,
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213 half addrspace(1)* %a) {
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214 entry:
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215 %a.val = load half, half addrspace(1)* %a
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216 %a.fabs = call half @llvm.fabs.f16(half %a.val)
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217 %r.val = fpext half %a.fabs to float
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218 %mul = fmul half %a.fabs, %a.val
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219 store volatile float %r.val, float addrspace(1)* %r
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220 store volatile half %mul, half addrspace(1)* undef
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221 ret void
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222 }
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223
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224 ; GCN-LABEL: {{^}}fabs_fneg_multi_use_fpext_f16_to_f32:
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225 ; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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226 ; GCN-DAG: v_or_b32_e32 [[OR:v[0-9]+]], 0x8000, [[A]]
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227
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228 ; SI: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], [[OR]]
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134
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229 ; GFX89-DAG: v_cvt_f32_f16_e64 [[CVT:v[0-9]+]], -|[[OR]]|
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121
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230
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231 ; GCN: buffer_store_dword [[CVT]]
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232 ; GCN: buffer_store_short [[OR]]
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233 define amdgpu_kernel void @fabs_fneg_multi_use_fpext_f16_to_f32(
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234 float addrspace(1)* %r,
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235 half addrspace(1)* %a) {
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236 entry:
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237 %a.val = load half, half addrspace(1)* %a
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238 %a.fabs = call half @llvm.fabs.f16(half %a.val)
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239 %a.fneg.fabs = fsub half -0.0, %a.fabs
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240 %r.val = fpext half %a.fneg.fabs to float
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241 store volatile float %r.val, float addrspace(1)* %r
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242 store volatile half %a.fneg.fabs, half addrspace(1)* undef
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243 ret void
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244 }
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245
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246 ; GCN-LABEL: {{^}}fabs_fneg_multi_foldable_use_fpext_f16_to_f32:
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247 ; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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248 ; SI: v_cvt_f32_f16_e32 [[CVTA:v[0-9]+]], [[A]]
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249 ; SI: v_mul_f32_e64 [[MUL_F32:v[0-9]+]], -|[[CVTA]]|, [[CVTA]]
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250 ; SI: v_cvt_f16_f32_e32 [[MUL:v[0-9]+]], [[MUL_F32]]
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251 ; SI: v_or_b32_e32 [[FABS_FNEG:v[0-9]+]], 0x80000000, [[CVTA]]
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252
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253 ; GFX89-DAG: v_cvt_f32_f16_e64 [[FABS_FNEG:v[0-9]+]], -|[[A]]|
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254 ; GFX89-DAG: v_mul_f16_e64 [[MUL:v[0-9]+]], -|[[A]]|, [[A]]
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255
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256 ; GCN: buffer_store_dword [[FABS_FNEG]]
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257 ; GCN: buffer_store_short [[MUL]]
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258 define amdgpu_kernel void @fabs_fneg_multi_foldable_use_fpext_f16_to_f32(
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259 float addrspace(1)* %r,
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260 half addrspace(1)* %a) {
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261 entry:
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262 %a.val = load half, half addrspace(1)* %a
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263 %a.fabs = call half @llvm.fabs.f16(half %a.val)
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264 %a.fneg.fabs = fsub half -0.0, %a.fabs
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265 %r.val = fpext half %a.fneg.fabs to float
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266 %mul = fmul half %a.fneg.fabs, %a.val
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267 store volatile float %r.val, float addrspace(1)* %r
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268 store volatile half %mul, half addrspace(1)* undef
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269 ret void
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270 }
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271
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272 declare half @llvm.fabs.f16(half) #1
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273
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274 attributes #1 = { nounwind readnone }
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