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annotate test/CodeGen/AMDGPU/llvm.log10.ll @ 146:3fc4d5c3e21e

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set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 3a76565eade5
children c2174574ed3a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
134
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1 ; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=FUNC %s
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3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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4 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
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5
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6 ; FUNC-LABEL: {{^}}test:
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7 ; EG: LOG_IEEE
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8 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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9 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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10 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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11 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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12 ; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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13 ; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
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14 define void @test(float addrspace(1)* %out, float %in) {
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15 entry:
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16 %res = call float @llvm.log10.f32(float %in)
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17 store float %res, float addrspace(1)* %out
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18 ret void
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19 }
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20
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21 ; FUNC-LABEL: {{^}}testv2:
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22 ; EG: LOG_IEEE
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23 ; EG: LOG_IEEE
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24 ; FIXME: We should be able to merge these packets together on Cayman so we
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25 ; have a maximum of 4 instructions.
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26 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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27 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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28 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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29 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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30 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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31 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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32 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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33 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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34 ; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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35 ; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
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36 ; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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37 ; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
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38 ; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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39 ; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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40 define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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41 entry:
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42 %res = call <2 x float> @llvm.log10.v2f32(<2 x float> %in)
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43 store <2 x float> %res, <2 x float> addrspace(1)* %out
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44 ret void
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45 }
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46
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47 ; FUNC-LABEL: {{^}}testv4:
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48 ; EG: LOG_IEEE
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49 ; EG: LOG_IEEE
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50 ; EG: LOG_IEEE
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51 ; EG: LOG_IEEE
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52 ; FIXME: We should be able to merge these packets together on Cayman so we
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53 ; have a maximum of 4 instructions.
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54 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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55 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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56 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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57 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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58 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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59 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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60 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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61 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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62 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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63 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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64 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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65 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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66 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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67 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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68 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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69 ; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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70 ; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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71 ; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
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72 ; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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73 ; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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74 ; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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75 ; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
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76 ; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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77 ; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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78 ; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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79 ; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
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80 define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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81 entry:
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82 %res = call <4 x float> @llvm.log10.v4f32(<4 x float> %in)
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83 store <4 x float> %res, <4 x float> addrspace(1)* %out
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84 ret void
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85 }
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86
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87 declare float @llvm.log10.f32(float) readnone
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88 declare <2 x float> @llvm.log10.v2f32(<2 x float>) readnone
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89 declare <4 x float> @llvm.log10.v4f32(<4 x float>) readnone