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annotate test/CodeGen/AMDGPU/operand-folding.ll @ 146:3fc4d5c3e21e

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set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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2
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3 ; CHECK-LABEL: {{^}}fold_sgpr:
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4 ; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s
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5 define amdgpu_kernel void @fold_sgpr(i32 addrspace(1)* %out, i32 %fold) {
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6 entry:
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7 %tmp0 = icmp ne i32 %fold, 0
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8 br i1 %tmp0, label %if, label %endif
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9
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10 if:
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11 %id = call i32 @llvm.amdgcn.workitem.id.x()
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12 %offset = add i32 %fold, %id
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13 %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %offset
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14 store i32 0, i32 addrspace(1)* %tmp1
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15 br label %endif
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16
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17 endif:
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18 ret void
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19 }
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20
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21 ; CHECK-LABEL: {{^}}fold_imm:
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22 ; CHECK: v_or_b32_e32 v{{[0-9]+}}, 5
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23 define amdgpu_kernel void @fold_imm(i32 addrspace(1)* %out, i32 %cmp) {
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24 entry:
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25 %fold = add i32 3, 2
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26 %tmp0 = icmp ne i32 %cmp, 0
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27 br i1 %tmp0, label %if, label %endif
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28
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29 if:
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30 %id = call i32 @llvm.amdgcn.workitem.id.x()
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31 %val = or i32 %id, %fold
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32 store i32 %val, i32 addrspace(1)* %out
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33 br label %endif
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34
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35 endif:
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36 ret void
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37 }
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38
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39 ; CHECK-LABEL: {{^}}fold_64bit_constant_add:
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40 ; CHECK-NOT: s_mov_b64
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41 ; FIXME: It would be better if we could use v_add here and drop the extra
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42 ; v_mov_b32 instructions.
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43 ; CHECK-DAG: s_add_u32 [[LO:s[0-9]+]], s{{[0-9]+}}, 1
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44 ; CHECK-DAG: s_addc_u32 [[HI:s[0-9]+]], s{{[0-9]+}}, 0
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45 ; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[LO]]
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46 ; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[HI]]
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47 ; CHECK: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}},
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48
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49 define amdgpu_kernel void @fold_64bit_constant_add(i64 addrspace(1)* %out, i32 %cmp, i64 %val) {
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50 entry:
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51 %tmp0 = add i64 %val, 1
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52 store i64 %tmp0, i64 addrspace(1)* %out
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53 ret void
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54 }
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55
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56 ; Inline constants should always be folded.
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57
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58 ; CHECK-LABEL: {{^}}vector_inline:
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59 ; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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60 ; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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61 ; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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62 ; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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63
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64 define amdgpu_kernel void @vector_inline(<4 x i32> addrspace(1)* %out) {
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65 entry:
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66 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x()
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67 %tmp1 = add i32 %tmp0, 1
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68 %tmp2 = add i32 %tmp0, 2
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69 %tmp3 = add i32 %tmp0, 3
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70 %vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
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71 %vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
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72 %vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
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73 %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
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74 %tmp4 = xor <4 x i32> <i32 5, i32 5, i32 5, i32 5>, %vec3
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75 store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
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76 ret void
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77 }
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78
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79 ; Immediates with one use should be folded
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80 ; CHECK-LABEL: {{^}}imm_one_use:
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81 ; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 0x64, v{{[0-9]+}}
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82
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83 define amdgpu_kernel void @imm_one_use(i32 addrspace(1)* %out) {
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84 entry:
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85 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x()
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86 %tmp1 = xor i32 %tmp0, 100
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87 store i32 %tmp1, i32 addrspace(1)* %out
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88 ret void
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89 }
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90 ; CHECK-LABEL: {{^}}vector_imm:
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91 ; CHECK: s_movk_i32 [[IMM:s[0-9]+]], 0x64
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92 ; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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93 ; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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94 ; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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95 ; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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97 define amdgpu_kernel void @vector_imm(<4 x i32> addrspace(1)* %out) {
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98 entry:
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99 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x()
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100 %tmp1 = add i32 %tmp0, 1
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101 %tmp2 = add i32 %tmp0, 2
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102 %tmp3 = add i32 %tmp0, 3
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103 %vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
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104 %vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
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105 %vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
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106 %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
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107 %tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3
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108 store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
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109 ret void
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110 }
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111
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112 ; A subregister use operand should not be tied.
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113 ; CHECK-LABEL: {{^}}no_fold_tied_subregister:
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114 ; CHECK: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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115 ; CHECK: v_mac_f32_e32 v[[LO]], 0x41200000, v[[HI]]
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116 ; CHECK: buffer_store_dword v[[LO]]
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117 define amdgpu_kernel void @no_fold_tied_subregister() {
120
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118 %tmp1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef
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119 %tmp2 = extractelement <2 x float> %tmp1, i32 0
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120 %tmp3 = extractelement <2 x float> %tmp1, i32 1
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121 %tmp4 = fmul float %tmp3, 10.0
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122 %tmp5 = fadd float %tmp4, %tmp2
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123 store volatile float %tmp5, float addrspace(1)* undef
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124 ret void
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125 }
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126
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127 declare i32 @llvm.amdgcn.workitem.id.x() #0
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128
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129 attributes #0 = { nounwind readnone }