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120
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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121
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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120
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3 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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100
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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4 ; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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5
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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6 ; FUNC-LABEL: {{^}}rcp_pat_f32:
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120
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7 ; GCN: s_load_dword [[SRC:s[0-9]+]]
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8 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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9 ; GCN: buffer_store_dword [[RCP]]
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10
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100
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff
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11 ; EG: RECIP_IEEE
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121
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12 define amdgpu_kernel void @rcp_pat_f32(float addrspace(1)* %out, float %src) #0 {
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100
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
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13 %rcp = fdiv float 1.0, %src
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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14 store float %rcp, float addrspace(1)* %out, align 4
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff
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15 ret void
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
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16 }
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120
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17
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18 ; FUNC-LABEL: {{^}}rcp_ulp25_pat_f32:
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19 ; GCN: s_load_dword [[SRC:s[0-9]+]]
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20 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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21 ; GCN: buffer_store_dword [[RCP]]
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22
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23 ; EG: RECIP_IEEE
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121
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24 define amdgpu_kernel void @rcp_ulp25_pat_f32(float addrspace(1)* %out, float %src) #0 {
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120
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25 %rcp = fdiv float 1.0, %src, !fpmath !0
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26 store float %rcp, float addrspace(1)* %out, align 4
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27 ret void
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28 }
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29
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30 ; FUNC-LABEL: {{^}}rcp_fast_ulp25_pat_f32:
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31 ; GCN: s_load_dword [[SRC:s[0-9]+]]
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32 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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33 ; GCN: buffer_store_dword [[RCP]]
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34
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35 ; EG: RECIP_IEEE
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121
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36 define amdgpu_kernel void @rcp_fast_ulp25_pat_f32(float addrspace(1)* %out, float %src) #0 {
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120
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37 %rcp = fdiv fast float 1.0, %src, !fpmath !0
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38 store float %rcp, float addrspace(1)* %out, align 4
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39 ret void
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40 }
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41
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42 ; FUNC-LABEL: {{^}}rcp_arcp_ulp25_pat_f32:
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43 ; GCN: s_load_dword [[SRC:s[0-9]+]]
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44 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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45 ; GCN: buffer_store_dword [[RCP]]
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46
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47 ; EG: RECIP_IEEE
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121
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48 define amdgpu_kernel void @rcp_arcp_ulp25_pat_f32(float addrspace(1)* %out, float %src) #0 {
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120
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49 %rcp = fdiv arcp float 1.0, %src, !fpmath !0
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50 store float %rcp, float addrspace(1)* %out, align 4
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51 ret void
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52 }
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53
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54 ; FUNC-LABEL: {{^}}rcp_global_fast_ulp25_pat_f32:
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55 ; GCN: s_load_dword [[SRC:s[0-9]+]]
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56 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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57 ; GCN: buffer_store_dword [[RCP]]
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58
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59 ; EG: RECIP_IEEE
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121
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60 define amdgpu_kernel void @rcp_global_fast_ulp25_pat_f32(float addrspace(1)* %out, float %src) #2 {
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120
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61 %rcp = fdiv float 1.0, %src, !fpmath !0
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62 store float %rcp, float addrspace(1)* %out, align 4
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63 ret void
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64 }
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65
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66 ; FUNC-LABEL: {{^}}rcp_fabs_pat_f32:
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67 ; GCN: s_load_dword [[SRC:s[0-9]+]]
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68 ; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], |[[SRC]]|
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69 ; GCN: buffer_store_dword [[RCP]]
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70
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71 ; EG: RECIP_IEEE
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121
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72 define amdgpu_kernel void @rcp_fabs_pat_f32(float addrspace(1)* %out, float %src) #0 {
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120
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73 %src.fabs = call float @llvm.fabs.f32(float %src)
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74 %rcp = fdiv float 1.0, %src.fabs
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75 store float %rcp, float addrspace(1)* %out, align 4
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76 ret void
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77 }
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78
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79 ; FUNC-LABEL: {{^}}neg_rcp_pat_f32:
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80 ; GCN: s_load_dword [[SRC:s[0-9]+]]
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81 ; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -[[SRC]]
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82 ; GCN: buffer_store_dword [[RCP]]
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83
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84 ; EG: RECIP_IEEE
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121
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85 define amdgpu_kernel void @neg_rcp_pat_f32(float addrspace(1)* %out, float %src) #0 {
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120
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86 %rcp = fdiv float -1.0, %src
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87 store float %rcp, float addrspace(1)* %out, align 4
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88 ret void
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89 }
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90
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91 ; FUNC-LABEL: {{^}}rcp_fabs_fneg_pat_f32:
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92 ; GCN: s_load_dword [[SRC:s[0-9]+]]
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93 ; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -|[[SRC]]|
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94 ; GCN: buffer_store_dword [[RCP]]
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121
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95 define amdgpu_kernel void @rcp_fabs_fneg_pat_f32(float addrspace(1)* %out, float %src) #0 {
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120
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96 %src.fabs = call float @llvm.fabs.f32(float %src)
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97 %src.fabs.fneg = fsub float -0.0, %src.fabs
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98 %rcp = fdiv float 1.0, %src.fabs.fneg
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99 store float %rcp, float addrspace(1)* %out, align 4
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100 ret void
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101 }
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102
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103 ; FUNC-LABEL: {{^}}rcp_fabs_fneg_pat_multi_use_f32:
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104 ; GCN: s_load_dword [[SRC:s[0-9]+]]
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105 ; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -|[[SRC]]|
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106 ; GCN: v_mul_f32_e64 [[MUL:v[0-9]+]], [[SRC]], -|[[SRC]]|
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107 ; GCN: buffer_store_dword [[RCP]]
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108 ; GCN: buffer_store_dword [[MUL]]
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121
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109 define amdgpu_kernel void @rcp_fabs_fneg_pat_multi_use_f32(float addrspace(1)* %out, float %src) #0 {
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120
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110 %src.fabs = call float @llvm.fabs.f32(float %src)
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111 %src.fabs.fneg = fsub float -0.0, %src.fabs
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112 %rcp = fdiv float 1.0, %src.fabs.fneg
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113 store volatile float %rcp, float addrspace(1)* %out, align 4
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114
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115 %other = fmul float %src, %src.fabs.fneg
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116 store volatile float %other, float addrspace(1)* %out, align 4
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117 ret void
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118 }
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119
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121
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120 ; FUNC-LABEL: {{^}}div_arcp_2_x_pat_f32:
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121 ; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], 0.5, v{{[0-9]+}}
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122 ; GCN: buffer_store_dword [[MUL]]
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123 define amdgpu_kernel void @div_arcp_2_x_pat_f32(float addrspace(1)* %out) #0 {
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124 %x = load float, float addrspace(1)* undef
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125 %rcp = fdiv arcp float %x, 2.0
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126 store float %rcp, float addrspace(1)* %out, align 4
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127 ret void
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128 }
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129
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130 ; FUNC-LABEL: {{^}}div_arcp_k_x_pat_f32:
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131 ; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], 0x3dcccccd, v{{[0-9]+}}
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132 ; GCN: buffer_store_dword [[MUL]]
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133 define amdgpu_kernel void @div_arcp_k_x_pat_f32(float addrspace(1)* %out) #0 {
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134 %x = load float, float addrspace(1)* undef
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135 %rcp = fdiv arcp float %x, 10.0
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136 store float %rcp, float addrspace(1)* %out, align 4
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137 ret void
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138 }
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139
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140 ; FUNC-LABEL: {{^}}div_arcp_neg_k_x_pat_f32:
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141 ; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], 0xbdcccccd, v{{[0-9]+}}
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142 ; GCN: buffer_store_dword [[MUL]]
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143 define amdgpu_kernel void @div_arcp_neg_k_x_pat_f32(float addrspace(1)* %out) #0 {
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144 %x = load float, float addrspace(1)* undef
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145 %rcp = fdiv arcp float %x, -10.0
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146 store float %rcp, float addrspace(1)* %out, align 4
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147 ret void
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148 }
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120
|
149
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150 declare float @llvm.fabs.f32(float) #1
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151 declare float @llvm.sqrt.f32(float) #1
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152
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153 attributes #0 = { nounwind "unsafe-fp-math"="false" }
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154 attributes #1 = { nounwind readnone }
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155 attributes #2 = { nounwind "unsafe-fp-math"="true" }
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156
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157 !0 = !{float 2.500000e+00}
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