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121
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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2
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3 ; GCN-LABEL: {{^}}setcc_sgt_true_sext:
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4 ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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5 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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6 ; GCN-NOT: v_cndmask_
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7
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8 define amdgpu_kernel void @setcc_sgt_true_sext(i32 addrspace(1)* nocapture %arg) {
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9 bb:
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10 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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11 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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12 %cmp = icmp ugt i32 %x, %y
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13 %ext = sext i1 %cmp to i32
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14 %cond = icmp sgt i32 %ext, -1
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15 br i1 %cond, label %then, label %endif
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16
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17 then:
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18 store i32 1, i32 addrspace(1)* %arg, align 4
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19 br label %endif
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20
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21 endif:
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22 ret void
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23 }
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24
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25 ; GCN-LABEL: {{^}}setcc_sgt_true_sext_swap:
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26 ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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27 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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28 ; GCN-NOT: v_cndmask_
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29
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30 define amdgpu_kernel void @setcc_sgt_true_sext_swap(i32 addrspace(1)* nocapture %arg) {
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31 bb:
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32 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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33 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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34 %cmp = icmp ugt i32 %x, %y
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35 %ext = sext i1 %cmp to i32
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36 %cond = icmp slt i32 -1, %ext
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37 br i1 %cond, label %then, label %endif
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38
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39 then:
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40 store i32 1, i32 addrspace(1)* %arg, align 4
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41 br label %endif
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42
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43 endif:
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44 ret void
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45 }
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46
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47 ; GCN-LABEL: {{^}}setcc_ne_true_sext:
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48 ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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49 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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50 ; GCN-NOT: v_cndmask_
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51
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52 define amdgpu_kernel void @setcc_ne_true_sext(i32 addrspace(1)* nocapture %arg) {
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53 bb:
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54 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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55 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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56 %cmp = icmp ugt i32 %x, %y
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57 %ext = sext i1 %cmp to i32
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58 %cond = icmp ne i32 %ext, -1
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59 br i1 %cond, label %then, label %endif
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60
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61 then:
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62 store i32 1, i32 addrspace(1)* %arg, align 4
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63 br label %endif
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64
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65 endif:
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66 ret void
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67 }
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68
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69 ; GCN-LABEL: {{^}}setcc_ult_true_sext:
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70 ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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71 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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72 ; GCN-NOT: v_cndmask_
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73
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74 define amdgpu_kernel void @setcc_ult_true_sext(i32 addrspace(1)* nocapture %arg) {
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75 bb:
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76 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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77 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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78 %cmp = icmp ugt i32 %x, %y
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79 %ext = sext i1 %cmp to i32
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80 %cond = icmp ult i32 %ext, -1
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81 br i1 %cond, label %then, label %endif
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82
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83 then:
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84 store i32 1, i32 addrspace(1)* %arg, align 4
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85 br label %endif
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86
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87 endif:
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88 ret void
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89 }
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90
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91 ; GCN-LABEL: {{^}}setcc_eq_true_sext:
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92 ; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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93 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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94 ; GCN-NOT: v_cndmask_
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95
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96 define amdgpu_kernel void @setcc_eq_true_sext(i32 addrspace(1)* nocapture %arg) {
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97 bb:
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98 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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99 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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100 %cmp = icmp ugt i32 %x, %y
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101 %ext = sext i1 %cmp to i32
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102 %cond = icmp eq i32 %ext, -1
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103 br i1 %cond, label %then, label %endif
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104
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105 then:
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106 store i32 1, i32 addrspace(1)* %arg, align 4
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107 br label %endif
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108
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109 endif:
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110 ret void
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111 }
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112
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113 ; GCN-LABEL: {{^}}setcc_sle_true_sext:
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114 ; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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115 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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116 ; GCN-NOT: v_cndmask_
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117
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118 define amdgpu_kernel void @setcc_sle_true_sext(i32 addrspace(1)* nocapture %arg) {
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119 bb:
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120 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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121 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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122 %cmp = icmp ugt i32 %x, %y
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123 %ext = sext i1 %cmp to i32
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124 %cond = icmp sle i32 %ext, -1
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125 br i1 %cond, label %then, label %endif
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126
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127 then:
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128 store i32 1, i32 addrspace(1)* %arg, align 4
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129 br label %endif
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130
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131 endif:
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132 ret void
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133 }
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134
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135 ; GCN-LABEL: {{^}}setcc_uge_true_sext:
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136 ; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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137 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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138 ; GCN-NOT: v_cndmask_
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139
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140 define amdgpu_kernel void @setcc_uge_true_sext(i32 addrspace(1)* nocapture %arg) {
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141 bb:
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142 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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143 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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144 %cmp = icmp ugt i32 %x, %y
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145 %ext = sext i1 %cmp to i32
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146 %cond = icmp uge i32 %ext, -1
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147 br i1 %cond, label %then, label %endif
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148
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149 then:
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150 store i32 1, i32 addrspace(1)* %arg, align 4
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151 br label %endif
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152
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153 endif:
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154 ret void
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155 }
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156
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157 ; GCN-LABEL: {{^}}setcc_eq_false_sext:
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158 ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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159 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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160 ; GCN-NOT: v_cndmask_
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161
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162 define amdgpu_kernel void @setcc_eq_false_sext(i32 addrspace(1)* nocapture %arg) {
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163 bb:
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164 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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165 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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166 %cmp = icmp ugt i32 %x, %y
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167 %ext = sext i1 %cmp to i32
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168 %cond = icmp eq i32 %ext, 0
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169 br i1 %cond, label %then, label %endif
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170
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171 then:
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172 store i32 1, i32 addrspace(1)* %arg, align 4
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173 br label %endif
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174
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175 endif:
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176 ret void
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177 }
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178
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179 ; GCN-LABEL: {{^}}setcc_sge_false_sext:
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180 ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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181 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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182 ; GCN-NOT: v_cndmask_
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183
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184 define amdgpu_kernel void @setcc_sge_false_sext(i32 addrspace(1)* nocapture %arg) {
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185 bb:
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186 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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187 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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188 %cmp = icmp ugt i32 %x, %y
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189 %ext = sext i1 %cmp to i32
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190 %cond = icmp sge i32 %ext, 0
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191 br i1 %cond, label %then, label %endif
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192
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193 then:
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194 store i32 1, i32 addrspace(1)* %arg, align 4
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195 br label %endif
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196
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197 endif:
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198 ret void
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199 }
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200
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201 ; GCN-LABEL: {{^}}setcc_ule_false_sext:
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202 ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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203 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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204 ; GCN-NOT: v_cndmask_
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205
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206 define amdgpu_kernel void @setcc_ule_false_sext(i32 addrspace(1)* nocapture %arg) {
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207 bb:
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208 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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209 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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210 %cmp = icmp ugt i32 %x, %y
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211 %ext = sext i1 %cmp to i32
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212 %cond = icmp ule i32 %ext, 0
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213 br i1 %cond, label %then, label %endif
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214
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215 then:
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216 store i32 1, i32 addrspace(1)* %arg, align 4
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217 br label %endif
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218
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219 endif:
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220 ret void
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221 }
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222
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223 ; GCN-LABEL: {{^}}setcc_ne_false_sext:
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224 ; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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225 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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226 ; GCN-NOT: v_cndmask_
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227
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228 define amdgpu_kernel void @setcc_ne_false_sext(i32 addrspace(1)* nocapture %arg) {
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229 bb:
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230 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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231 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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232 %cmp = icmp ugt i32 %x, %y
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233 %ext = sext i1 %cmp to i32
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234 %cond = icmp ne i32 %ext, 0
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235 br i1 %cond, label %then, label %endif
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236
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237 then:
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238 store i32 1, i32 addrspace(1)* %arg, align 4
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239 br label %endif
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240
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241 endif:
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242 ret void
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243 }
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244 ; GCN-LABEL: {{^}}setcc_ugt_false_sext:
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245 ; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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246 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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247 ; GCN-NOT: v_cndmask_
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248
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249 define amdgpu_kernel void @setcc_ugt_false_sext(i32 addrspace(1)* nocapture %arg) {
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250 bb:
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251 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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252 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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253 %cmp = icmp ugt i32 %x, %y
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254 %ext = sext i1 %cmp to i32
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255 %cond = icmp ugt i32 %ext, 0
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256 br i1 %cond, label %then, label %endif
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257
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258 then:
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259 store i32 1, i32 addrspace(1)* %arg, align 4
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260 br label %endif
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261
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262 endif:
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263 ret void
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264 }
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265 ; GCN-LABEL: {{^}}setcc_slt_false_sext:
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266 ; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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267 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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268 ; GCN-NOT: v_cndmask_
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269
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270 define amdgpu_kernel void @setcc_slt_false_sext(i32 addrspace(1)* nocapture %arg) {
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271 bb:
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272 %x = tail call i32 @llvm.amdgcn.workitem.id.x()
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273 %y = tail call i32 @llvm.amdgcn.workitem.id.y()
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274 %cmp = icmp ugt i32 %x, %y
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275 %ext = sext i1 %cmp to i32
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276 %cond = icmp slt i32 %ext, 0
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277 br i1 %cond, label %then, label %endif
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278
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279 then:
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280 store i32 1, i32 addrspace(1)* %arg, align 4
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281 br label %endif
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282
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283 endif:
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284 ret void
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285 }
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286
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287
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288 declare i32 @llvm.amdgcn.workitem.id.x() #0
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289
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290 declare i32 @llvm.amdgcn.workitem.id.y() #0
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291
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292 attributes #0 = { nounwind readnone speculatable }
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