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1 ; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR %s
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2 ; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SMEM %s
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3 ; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VMEM %s
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4
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5 ; ALL-LABEL: {{^}}spill_sgpr_x2:
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6 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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7 ; SMEM: s_buffer_store_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[8:11], m0 ; 8-byte Folded Spill
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8 ; SMEM: s_cbranch_scc1
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9
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10 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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11 ; SMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[8:11], m0 ; 8-byte Folded Reload
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12
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13 ; SMEM: s_dcache_wb
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14 ; SMEM: s_endpgm
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15
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16 ; FIXME: Should only need 4 bytes
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17 ; SMEM: ScratchSize: 12
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18
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19
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20 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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21 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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22 ; VGPR: s_cbranch_scc1
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23
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24 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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25 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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26
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27 ; VMEM: buffer_store_dword
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28 ; VMEM: buffer_store_dword
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29 ; VMEM: s_cbranch_scc1
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30
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31 ; VMEM: buffer_load_dword
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32 ; VMEM: buffer_load_dword
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33 define amdgpu_kernel void @spill_sgpr_x2(i32 addrspace(1)* %out, i32 %in) #0 {
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34 %wide.sgpr = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
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35 %cmp = icmp eq i32 %in, 0
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36 br i1 %cmp, label %bb0, label %ret
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37
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38 bb0:
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39 call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr) #0
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40 br label %ret
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41
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42 ret:
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43 ret void
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44 }
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45
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46 ; ALL-LABEL: {{^}}spill_sgpr_x4:
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47 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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48 ; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[12:15], m0 ; 16-byte Folded Spill
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49 ; SMEM: s_cbranch_scc1
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50
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51 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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52 ; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[12:15], m0 ; 16-byte Folded Reload
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53 ; SMEM: s_dcache_wb
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54 ; SMEM: s_endpgm
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55
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56 ; FIXME: Should only need 4 bytes
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57 ; SMEM: ScratchSize: 20
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58
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59 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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60 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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61 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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63 ; VGPR: s_cbranch_scc1
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64
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65 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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66 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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67 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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69
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70
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71 ; VMEM: buffer_store_dword
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72 ; VMEM: buffer_store_dword
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73 ; VMEM: buffer_store_dword
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74 ; VMEM: buffer_store_dword
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75 ; VMEM: s_cbranch_scc1
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76
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77 ; VMEM: buffer_load_dword
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78 ; VMEM: buffer_load_dword
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79 ; VMEM: buffer_load_dword
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80 ; VMEM: buffer_load_dword
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81 define amdgpu_kernel void @spill_sgpr_x4(i32 addrspace(1)* %out, i32 %in) #0 {
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82 %wide.sgpr = call <4 x i32> asm sideeffect "; def $0", "=s" () #0
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83 %cmp = icmp eq i32 %in, 0
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84 br i1 %cmp, label %bb0, label %ret
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85
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86 bb0:
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87 call void asm sideeffect "; use $0", "s"(<4 x i32> %wide.sgpr) #0
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88 br label %ret
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89
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90 ret:
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91 ret void
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92 }
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93
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94 ; ALL-LABEL: {{^}}spill_sgpr_x8:
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95
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96 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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97 ; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[16:19], m0 ; 16-byte Folded Spill
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98 ; SMEM: s_add_u32 m0, s3, 0x110{{$}}
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99 ; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[16:19], m0 ; 16-byte Folded Spill
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100 ; SMEM: s_cbranch_scc1
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101
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102 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
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103 ; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[16:19], m0 ; 16-byte Folded Reload
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104 ; SMEM: s_add_u32 m0, s3, 0x110{{$}}
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105 ; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[16:19], m0 ; 16-byte Folded Reload
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106
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107 ; SMEM: s_dcache_wb
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108 ; SMEM: s_endpgm
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109
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110 ; SMEM: ScratchSize: 36
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111
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112 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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113 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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114 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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115 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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116 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
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117 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5
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118 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6
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119 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7
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120 ; VGPR: s_cbranch_scc1
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121
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122 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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123 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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124 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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125 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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126 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
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127 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5
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128 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6
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129 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7
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130
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131 ; VMEM: buffer_store_dword
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132 ; VMEM: buffer_store_dword
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133 ; VMEM: buffer_store_dword
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134 ; VMEM: buffer_store_dword
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135 ; VMEM: buffer_store_dword
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136 ; VMEM: buffer_store_dword
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137 ; VMEM: buffer_store_dword
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138 ; VMEM: buffer_store_dword
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139 ; VMEM: s_cbranch_scc1
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140
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141 ; VMEM: buffer_load_dword
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142 ; VMEM: buffer_load_dword
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143 ; VMEM: buffer_load_dword
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144 ; VMEM: buffer_load_dword
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145 ; VMEM: buffer_load_dword
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146 ; VMEM: buffer_load_dword
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147 ; VMEM: buffer_load_dword
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148 ; VMEM: buffer_load_dword
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149 define amdgpu_kernel void @spill_sgpr_x8(i32 addrspace(1)* %out, i32 %in) #0 {
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150 %wide.sgpr = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
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151 %cmp = icmp eq i32 %in, 0
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152 br i1 %cmp, label %bb0, label %ret
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153
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154 bb0:
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155 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr) #0
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156 br label %ret
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157
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158 ret:
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159 ret void
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160 }
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161
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162 ; FIXME: x16 inlineasm seems broken
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163 ; define amdgpu_kernel void @spill_sgpr_x16(i32 addrspace(1)* %out, i32 %in) #0 {
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164 ; %wide.sgpr = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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165 ; %cmp = icmp eq i32 %in, 0
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166 ; br i1 %cmp, label %bb0, label %ret
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167
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168 ; bb0:
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169 ; call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr) #0
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170 ; br label %ret
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171
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172 ; ret:
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173 ; ret void
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174 ; }
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175
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176 attributes #0 = { nounwind }
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