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121
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1 ; RUN: llc -march=arc < %s | FileCheck %s
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2
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3 ; CHECK-LABEL: add_r
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4 ; CHECK: add %r0, %r{{[01]}}, %r{{[01]}}
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5 define i32 @add_r(i32 %a, i32 %b) nounwind {
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6 entry:
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7 %v = add i32 %a, %b
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8 ret i32 %v
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9 }
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10
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11 ; CHECK-LABEL: add_u6
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12 ; CHECK: add %r0, %r0, 15
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13 define i32 @add_u6(i32 %a) nounwind {
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14 %v = add i32 %a, 15
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15 ret i32 %v
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16 }
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17
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18 ; CHECK-LABEL: add_limm
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19 ; CHECK: add %r0, %r0, 12345
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20 define i32 @add_limm(i32 %a) nounwind {
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21 %v = add i32 %a, 12345
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22 ret i32 %v
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23 }
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24
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25 ; CHECK-LABEL: mpy_r
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26 ; CHECK: mpy %r0, %r{{[01]}}, %r{{[01]}}
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27 define i32 @mpy_r(i32 %a, i32 %b) nounwind {
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28 entry:
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29 %v = mul i32 %a, %b
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30 ret i32 %v
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31 }
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32
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33 ; CHECK-LABEL: mpy_u6
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34 ; CHECK: mpy %r0, %r0, 10
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35 define i32 @mpy_u6(i32 %a) nounwind {
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36 %v = mul i32 %a, 10
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37 ret i32 %v
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38 }
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39
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40 ; CHECK-LABEL: mpy_limm
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41 ; CHECK: mpy %r0, %r0, 12345
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42 define i32 @mpy_limm(i32 %a) nounwind {
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43 %v = mul i32 %a, 12345
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44 ret i32 %v
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45 }
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46
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47 ; CHECK-LABEL: max_r
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48 ; CHECK: max %r0, %r{{[01]}}, %r{{[01]}}
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49 define i32 @max_r(i32 %a, i32 %b) nounwind {
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50 %i = icmp sgt i32 %a, %b
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51 %v = select i1 %i, i32 %a, i32 %b
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52 ret i32 %v
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53 }
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54
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55 ; CHECK-LABEL: max_u6
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56 ; CHECK: max %r0, %r0, 12
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57 define i32 @max_u6(i32 %a) nounwind {
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58 %i = icmp sgt i32 %a, 12
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59 %v = select i1 %i, i32 %a, i32 12
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60 ret i32 %v
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61 }
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62
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63 ; CHECK-LABEL: max_limm
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64 ; CHECK: max %r0, %r0, 2345
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65 define i32 @max_limm(i32 %a) nounwind {
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66 %i = icmp sgt i32 %a, 2345
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67 %v = select i1 %i, i32 %a, i32 2345
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68 ret i32 %v
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69 }
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70
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71 ; CHECK-LABEL: min_r
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72 ; CHECK: min %r0, %r{{[01]}}, %r{{[01]}}
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73 define i32 @min_r(i32 %a, i32 %b) nounwind {
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74 %i = icmp slt i32 %a, %b
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75 %v = select i1 %i, i32 %a, i32 %b
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76 ret i32 %v
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77 }
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78
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79 ; CHECK-LABEL: min_u6
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80 ; CHECK: min %r0, %r0, 20
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81 define i32 @min_u6(i32 %a) nounwind {
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82 %i = icmp slt i32 %a, 20
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83 %v = select i1 %i, i32 %a, i32 20
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84 ret i32 %v
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85 }
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86
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87 ; CHECK-LABEL: min_limm
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88 ; CHECK: min %r0, %r0, 2040
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89 define i32 @min_limm(i32 %a) nounwind {
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90 %i = icmp slt i32 %a, 2040
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91 %v = select i1 %i, i32 %a, i32 2040
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92 ret i32 %v
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93 }
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94
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95 ; CHECK-LABEL: and_r
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96 ; CHECK: and %r0, %r{{[01]}}, %r{{[01]}}
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97 define i32 @and_r(i32 %a, i32 %b) nounwind {
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98 %v = and i32 %a, %b
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99 ret i32 %v
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100 }
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101
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102 ; CHECK-LABEL: and_u6
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103 ; CHECK: and %r0, %r0, 7
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104 define i32 @and_u6(i32 %a) nounwind {
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105 %v = and i32 %a, 7
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106 ret i32 %v
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107 }
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108
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109 ; 0xfffff == 1048575
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110 ; CHECK-LABEL: and_limm
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111 ; CHECK: and %r0, %r0, 1048575
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112 define i32 @and_limm(i32 %a) nounwind {
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113 %v = and i32 %a, 1048575
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114 ret i32 %v
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115 }
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116
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117 ; CHECK-LABEL: or_r
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118 ; CHECK: or %r0, %r{{[01]}}, %r{{[01]}}
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119 define i32 @or_r(i32 %a, i32 %b) nounwind {
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120 %v = or i32 %a, %b
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121 ret i32 %v
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122 }
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123
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124 ; CHECK-LABEL: or_u6
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125 ; CHECK: or %r0, %r0, 7
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126 define i32 @or_u6(i32 %a) nounwind {
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127 %v = or i32 %a, 7
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128 ret i32 %v
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129 }
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130
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131 ; 0xf0f0f == 986895
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132 ; CHECK-LABEL: or_limm
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133 define i32 @or_limm(i32 %a) nounwind {
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134 %v = or i32 %a, 986895
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135 ret i32 %v
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136 }
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137
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138 ; CHECK-LABEL: xor_r
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139 ; CHECK: xor %r0, %r{{[01]}}, %r{{[01]}}
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140 define i32 @xor_r(i32 %a, i32 %b) nounwind {
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141 %v = xor i32 %a, %b
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142 ret i32 %v
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143 }
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144
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145 ; CHECK-LABEL: xor_u6
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146 ; CHECK: xor %r0, %r0, 3
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147 define i32 @xor_u6(i32 %a) nounwind {
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148 %v = xor i32 %a, 3
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149 ret i32 %v
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150 }
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151
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152 ; CHECK-LABEL: xor_limm
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153 ; CHECK: xor %r0, %r0, 986895
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154 define i32 @xor_limm(i32 %a) nounwind {
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155 %v = xor i32 %a, 986895
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156 ret i32 %v
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157 }
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158
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159 ; CHECK-LABEL: asl_r
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160 ; CHECK: asl %r0, %r{{[01]}}, %r{{[01]}}
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161 define i32 @asl_r(i32 %a, i32 %b) nounwind {
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162 %v = shl i32 %a, %b
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163 ret i32 %v
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164 }
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165
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166 ; CHECK-LABEL: asl_u6
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167 ; CHECK: asl %r0, %r0, 4
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168 define i32 @asl_u6(i32 %a) nounwind {
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169 %v = shl i32 %a, 4
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170 ret i32 %v
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171 }
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172
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173 ; CHECK-LABEL: lsr_r
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174 ; CHECK: lsr %r0, %r{{[01]}}, %r{{[01]}}
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175 define i32 @lsr_r(i32 %a, i32 %b) nounwind {
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176 %v = lshr i32 %a, %b
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177 ret i32 %v
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178 }
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179
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180 ; CHECK-LABEL: lsr_u6
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181 ; CHECK: lsr %r0, %r0, 6
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182 define i32 @lsr_u6(i32 %a) nounwind {
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183 %v = lshr i32 %a, 6
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184 ret i32 %v
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185 }
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186
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187 ; CHECK-LABEL: asr_r
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188 ; CHECK: asr %r0, %r{{[01]}}, %r{{[01]}}
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189 define i32 @asr_r(i32 %a, i32 %b) nounwind {
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190 %v = ashr i32 %a, %b
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191 ret i32 %v
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192 }
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193
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194 ; CHECK-LABEL: asr_u6
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195 ; CHECK: asr %r0, %r0, 8
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196 define i32 @asr_u6(i32 %a) nounwind {
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197 %v = ashr i32 %a, 8
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198 ret i32 %v
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199 }
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200
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201 ; CHECK-LABEL: ror_r
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202 ; CHECK: ror %r0, %r{{[01]}}, %r{{[01]}}
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203 define i32 @ror_r(i32 %a, i32 %b) nounwind {
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204 %v1 = lshr i32 %a, %b
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205 %ls = sub i32 32, %b
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206 %v2 = shl i32 %a, %ls
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207 %v = or i32 %v1, %v2
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208 ret i32 %v
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209 }
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210
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211 ; CHECK-LABEL: ror_u6
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212 ; CHECK: ror %r0, %r0, 10
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213 define i32 @ror_u6(i32 %a) nounwind {
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214 %v1 = lshr i32 %a, 10
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215 %v2 = shl i32 %a, 22
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216 %v = or i32 %v1, %v2
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217 ret i32 %v
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218 }
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219
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220 ; CHECK-LABEL: sexh_r
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221 ; CHECK: sexh %r0, %r0
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222 define i32 @sexh_r(i32 %a) nounwind {
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223 %v1 = shl i32 %a, 16
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224 %v = ashr i32 %v1, 16
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225 ret i32 %v
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226 }
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227
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228 ; CHECK-LABEL: sexb_r
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229 ; CHECK: sexb %r0, %r0
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230 define i32 @sexb_r(i32 %a) nounwind {
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231 %v1 = shl i32 %a, 24
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232 %v = ashr i32 %v1, 24
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233 ret i32 %v
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234 }
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235
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236 ; CHECK-LABEL: mulu64
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237 ; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
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238 ; CHECK-DAG: mpymu %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
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239 define i64 @mulu64(i32 %a, i32 %b) nounwind {
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240 %a64 = zext i32 %a to i64
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241 %b64 = zext i32 %b to i64
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242 %v = mul i64 %a64, %b64
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243 ret i64 %v
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244 }
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245
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246 ; CHECK-LABEL: muls64
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247 ; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
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248 ; CHECK-DAG: mpym %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
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249 define i64 @muls64(i32 %a, i32 %b) nounwind {
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250 %a64 = sext i32 %a to i64
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251 %b64 = sext i32 %b to i64
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252 %v = mul i64 %a64, %b64
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253 ret i64 %v
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254 }
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255
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