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121
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1 ; RUN: llc -march=arc < %s | FileCheck %s
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2
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3 ; CHECK-LABEL: load32
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4 ; CHECK: ld %r0, [%r0,16000]
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5
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6 define i32 @load32(i32* %bp) nounwind {
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7 entry:
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8 %gep = getelementptr i32, i32* %bp, i32 4000
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9 %v = load i32, i32* %gep, align 4
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10 ret i32 %v
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11 }
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12
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13 ; CHECK-LABEL: load16
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14 ; CHECK: ldh %r0, [%r0,8000]
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15
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16 define i16 @load16(i16* %bp) nounwind {
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17 entry:
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18 %gep = getelementptr i16, i16* %bp, i32 4000
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19 %v = load i16, i16* %gep, align 2
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20 ret i16 %v
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21 }
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22
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23 ; CHECK-LABEL: load8
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24 ; CHECK: ldb %r0, [%r0,4000]
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25
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26 define i8 @load8(i8* %bp) nounwind {
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27 entry:
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28 %gep = getelementptr i8, i8* %bp, i32 4000
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29 %v = load i8, i8* %gep, align 1
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30 ret i8 %v
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31 }
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32
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33 ; CHECK-LABEL: sextload16
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34 ; CHECK: ldh.x %r0, [%r0,8000]
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35
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36 define i32 @sextload16(i16* %bp) nounwind {
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37 entry:
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38 %gep = getelementptr i16, i16* %bp, i32 4000
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39 %vl = load i16, i16* %gep, align 2
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40 %v = sext i16 %vl to i32
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41 ret i32 %v
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42 }
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43
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44 ; CHECK-LABEL: sextload8
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45 ; CHECK: ldb.x %r0, [%r0,4000]
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46
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47 define i32 @sextload8(i8* %bp) nounwind {
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48 entry:
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49 %gep = getelementptr i8, i8* %bp, i32 4000
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50 %vl = load i8, i8* %gep, align 1
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51 %v = sext i8 %vl to i32
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52 ret i32 %v
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53 }
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54
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55 ; CHECK-LABEL: s_sextload16
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56 ; CHECK: ldh.x %r0, [%r0,32]
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57
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58 define i32 @s_sextload16(i16* %bp) nounwind {
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59 entry:
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60 %gep = getelementptr i16, i16* %bp, i32 16
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61 %vl = load i16, i16* %gep, align 2
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62 %v = sext i16 %vl to i32
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63 ret i32 %v
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64 }
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65
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66 ; CHECK-LABEL: s_sextload8
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67 ; CHECK: ldb.x %r0, [%r0,16]
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68
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69 define i32 @s_sextload8(i8* %bp) nounwind {
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70 entry:
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71 %gep = getelementptr i8, i8* %bp, i32 16
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72 %vl = load i8, i8* %gep, align 1
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73 %v = sext i8 %vl to i32
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74 ret i32 %v
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75 }
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76
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77 ; CHECK-LABEL: store32
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78 ; CHECK: add %r[[REG:[0-9]+]], %r1, 16000
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79 ; CHECK: st %r0, [%r[[REG]],0]
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80
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81 ; Long range stores (offset does not fit in s9) must be add followed by st.
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82 define void @store32(i32 %val, i32* %bp) nounwind {
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83 entry:
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84 %gep = getelementptr i32, i32* %bp, i32 4000
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85 store i32 %val, i32* %gep, align 4
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86 ret void
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87 }
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88
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89 ; CHECK-LABEL: store16
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90 ; CHECK: add %r[[REG:[0-9]+]], %r1, 8000
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91 ; CHECK: sth %r0, [%r[[REG]],0]
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92
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93 define void @store16(i16 zeroext %val, i16* %bp) nounwind {
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94 entry:
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95 %gep = getelementptr i16, i16* %bp, i32 4000
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96 store i16 %val, i16* %gep, align 2
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97 ret void
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98 }
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99
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100 ; CHECK-LABEL: store8
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101 ; CHECK: add %r[[REG:[0-9]+]], %r1, 4000
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102 ; CHECK: stb %r0, [%r[[REG]],0]
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103
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104 define void @store8(i8 zeroext %val, i8* %bp) nounwind {
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105 entry:
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106 %gep = getelementptr i8, i8* %bp, i32 4000
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107 store i8 %val, i8* %gep, align 1
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108 ret void
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109 }
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110
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111 ; Short range stores can be done with [reg, s9].
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112 ; CHECK-LABEL: s_store32
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113 ; CHECK-NOT: add
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114 ; CHECK: st %r0, [%r1,64]
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115 define void @s_store32(i32 %val, i32* %bp) nounwind {
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116 entry:
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117 %gep = getelementptr i32, i32* %bp, i32 16
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118 store i32 %val, i32* %gep, align 4
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119 ret void
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120 }
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121
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122 ; CHECK-LABEL: s_store16
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123 ; CHECK-NOT: add
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124 ; CHECK: sth %r0, [%r1,32]
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125 define void @s_store16(i16 zeroext %val, i16* %bp) nounwind {
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126 entry:
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127 %gep = getelementptr i16, i16* %bp, i32 16
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128 store i16 %val, i16* %gep, align 2
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129 ret void
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130 }
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131
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132 ; CHECK-LABEL: s_store8
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133 ; CHECK-NOT: add
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134 ; CHECK: stb %r0, [%r1,16]
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135 define void @s_store8(i8 zeroext %val, i8* %bp) nounwind {
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136 entry:
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137 %gep = getelementptr i8, i8* %bp, i32 16
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138 store i8 %val, i8* %gep, align 1
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139 ret void
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140 }
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141
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142
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143 @aaaa = internal global [128 x i32] zeroinitializer
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144 @bbbb = internal global [128 x i16] zeroinitializer
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145 @cccc = internal global [128 x i8] zeroinitializer
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146
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147 ; CHECK-LABEL: g_store32
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148 ; CHECK-NOT: add
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149 ; CHECK: st %r0, [@aaaa+64]
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150 define void @g_store32(i32 %val) nounwind {
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151 entry:
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152 store i32 %val, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @aaaa, i32 0, i32 16), align 4
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153 ret void
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154 }
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155
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156 ; CHECK-LABEL: g_load32
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157 ; CHECK-NOT: add
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158 ; CHECK: ld %r0, [@aaaa+64]
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159 define i32 @g_load32() nounwind {
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160 %gep = getelementptr inbounds [128 x i32], [128 x i32]* @aaaa, i32 0, i32 16
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161 %v = load i32, i32* %gep, align 4
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162 ret i32 %v
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163 }
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164
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165 ; CHECK-LABEL: g_store16
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166 ; CHECK-NOT: add
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167 ; CHECK: sth %r0, [@bbbb+32]
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168 define void @g_store16(i16 %val) nounwind {
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169 entry:
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170 store i16 %val, i16* getelementptr inbounds ([128 x i16], [128 x i16]* @bbbb, i16 0, i16 16), align 2
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171 ret void
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172 }
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173
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174 ; CHECK-LABEL: g_load16
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175 ; CHECK-NOT: add
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176 ; CHECK: ldh %r0, [@bbbb+32]
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177 define i16 @g_load16() nounwind {
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178 %gep = getelementptr inbounds [128 x i16], [128 x i16]* @bbbb, i16 0, i16 16
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179 %v = load i16, i16* %gep, align 2
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180 ret i16 %v
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181 }
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182
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183 ; CHECK-LABEL: g_store8
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184 ; CHECK-NOT: add
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185 ; CHECK: stb %r0, [@cccc+16]
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186 define void @g_store8(i8 %val) nounwind {
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187 entry:
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188 store i8 %val, i8* getelementptr inbounds ([128 x i8], [128 x i8]* @cccc, i8 0, i8 16), align 1
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189 ret void
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190 }
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191
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192 ; CHECK-LABEL: g_load8
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193 ; CHECK-NOT: add
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194 ; CHECK: ldb %r0, [@cccc+16]
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195 define i8 @g_load8() nounwind {
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196 %gep = getelementptr inbounds [128 x i8], [128 x i8]* @cccc, i8 0, i8 16
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197 %v = load i8, i8* %gep, align 1
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198 ret i8 %v
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199 }
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200
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201 ; CHECK-LABEL: align2_load32
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202 ; CHECK-DAG: ldh %r[[REG0:[0-9]+]], [%r0,0]
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203 ; CHECK-DAG: ldh %r[[REG1:[0-9]+]], [%r0,2]
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204 ; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 16
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205 define i32 @align2_load32(i8* %p) nounwind {
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206 entry:
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207 %bp = bitcast i8* %p to i32*
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208 %v = load i32, i32* %bp, align 2
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209 ret i32 %v
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210 }
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211
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212 ; CHECK-LABEL: align1_load32
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213 ; CHECK-DAG: ldb %r[[REG0:[0-9]+]], [%r0,0]
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214 ; CHECK-DAG: ldb %r[[REG1:[0-9]+]], [%r0,1]
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215 ; CHECK-DAG: ldb %r[[REG2:[0-9]+]], [%r0,2]
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216 ; CHECK-DAG: ldb %r[[REG3:[0-9]+]], [%r0,3]
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217 ; CHECK-DAG: asl %r[[AREG1:[0-9]+]], %r[[REG1]], 8
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218 ; CHECK-DAG: asl %r[[AREG3:[0-9]+]], %r[[REG3]], 8
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219 define i32 @align1_load32(i8* %p) nounwind {
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220 entry:
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221 %bp = bitcast i8* %p to i32*
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222 %v = load i32, i32* %bp, align 1
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223 ret i32 %v
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224 }
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225
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226 ; CHECK-LABEL: align1_load16
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227 ; CHECK-DAG: ldb %r[[REG0:[0-9]+]], [%r0,0]
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228 ; CHECK-DAG: ldb %r[[REG1:[0-9]+]], [%r0,1]
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229 ; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 8
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230 define i16 @align1_load16(i8* %p) nounwind {
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231 entry:
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232 %bp = bitcast i8* %p to i16*
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233 %v = load i16, i16* %bp, align 1
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234 ret i16 %v
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235 }
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236
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237 ; CHECK-LABEL: align2_store32
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238 ; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 16
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239 ; CHECK-DAG: sth %r1, [%r0,0]
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240 ; CHECK-DAG: sth %r[[REG:[0-9]+]], [%r0,2]
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241 define void @align2_store32(i8* %p, i32 %v) nounwind {
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242 entry:
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243 %bp = bitcast i8* %p to i32*
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244 store i32 %v, i32* %bp, align 2
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245 ret void
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246 }
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247
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248 ; CHECK-LABEL: align1_store16
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249 ; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 8
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250 ; CHECK-DAG: stb %r1, [%r0,0]
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251 ; CHECK-DAG: stb %r[[REG:[0-9]+]], [%r0,1]
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252 define void @align1_store16(i8* %p, i16 %v) nounwind {
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253 entry:
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254 %bp = bitcast i8* %p to i16*
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255 store i16 %v, i16* %bp, align 1
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256 ret void
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257 }
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258
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259 ; CHECK-LABEL: align1_store32
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260 ; CHECK-DAG: lsr %r[[REG0:[0-9]+]], %r1, 8
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261 ; CHECK-DAG: lsr %r[[REG1:[0-9]+]], %r1, 16
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262 ; CHECK-DAG: lsr %r[[REG2:[0-9]+]], %r1, 24
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263 ; CHECK-DAG: stb %r1, [%r0,0]
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264 ; CHECK-DAG: stb %r[[REG0]], [%r0,1]
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265 ; CHECK-DAG: stb %r[[REG1]], [%r0,2]
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266 ; CHECK-DAG: stb %r[[REG2]], [%r0,3]
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267 define void @align1_store32(i8* %p, i32 %v) nounwind {
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268 entry:
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269 %bp = bitcast i8* %p to i32*
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270 store i32 %v, i32* %bp, align 1
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271 ret void
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272 }
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