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annotate test/CodeGen/Hexagon/avoid-predspill.ll @ 146:3fc4d5c3e21e

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set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 7d135dc70f03
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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2 ;
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3 ; This checks that predicate registers are moved to GPRs instead of spilling
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4 ; where possible.
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5
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6 ; CHECK: p0 =
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7 ; CHECK-NOT: memw(r29
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8
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9 define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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10 entry:
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11 %cmp = icmp eq i32 %a, 1
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12 %cmp1 = icmp eq i32 %b, 2
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13 %or.cond = and i1 %cmp, %cmp1
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14 %cmp3 = icmp eq i32 %c, 3
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15 %or.cond30 = and i1 %or.cond, %cmp3
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16 %cmp5 = icmp eq i32 %d, 4
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17 %or.cond31 = and i1 %or.cond30, %cmp5
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18 %cmp7 = icmp eq i32 %e, 5
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19 %or.cond32 = and i1 %or.cond31, %cmp7
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20 %ret.0 = zext i1 %or.cond32 to i32
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21 %cmp8 = icmp eq i32 %a, 3
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22 %cmp10 = icmp eq i32 %b, 4
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23 %or.cond33 = and i1 %cmp8, %cmp10
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24 %cmp12 = icmp eq i32 %c, 5
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25 %or.cond34 = and i1 %or.cond33, %cmp12
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26 %cmp14 = icmp eq i32 %d, 6
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27 %or.cond35 = and i1 %or.cond34, %cmp14
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28 %cmp16 = icmp eq i32 %e, 7
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29 %or.cond36 = and i1 %or.cond35, %cmp16
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30 %ret.1 = select i1 %or.cond36, i32 2, i32 %ret.0
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31 %cmp21 = icmp eq i32 %b, 8
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32 %or.cond37 = and i1 %cmp, %cmp21
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33 %cmp23 = icmp eq i32 %c, 2
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34 %or.cond38 = and i1 %or.cond37, %cmp23
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35 %cmp25 = icmp eq i32 %d, 1
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36 %or.cond39 = and i1 %or.cond38, %cmp25
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37 %cmp27 = icmp eq i32 %e, 3
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38 %or.cond40 = and i1 %or.cond39, %cmp27
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39 %ret.2 = select i1 %or.cond40, i32 3, i32 %ret.1
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40 ret i32 %ret.2
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41 }
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42