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annotate test/CodeGen/Hexagon/early-if-vecpred.ll @ 146:3fc4d5c3e21e

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set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; RUN: llc -march=hexagon < %s | FileCheck %s
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2 ; REQUIRES: asserts
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3
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4 ; Hexagon early if-conversion used to crash on this testcase due to not
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5 ; recognizing vector predicate registers.
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6
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7 target triple = "hexagon"
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8
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9 ; Check that the early if-conversion has not happened.
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10
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11 ; CHECK-LABEL: fred
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12 ; CHECK: q{{[0-3]}} = not
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13 ; CHECK: LBB
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14 ; CHECK: if (q{{[0-3]}}) vmem
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15 define void @fred(i32 %a0) #0 {
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16 b1:
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17 %v2 = tail call <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %a0) #2
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18 br i1 undef, label %b3, label %b5
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19
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20 b3: ; preds = %b1
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21 %v4 = tail call <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1> %v2) #2
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22 br label %b5
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23
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24 b5: ; preds = %b3, %b1
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25 %v6 = phi <1024 x i1> [ %v4, %b3 ], [ %v2, %b1 ]
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26 %v7 = bitcast <1024 x i1> %v6 to <32 x i32>
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27 tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<32 x i32> %v7, <32 x i32>* undef, <32 x i32> undef) #2
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28 ret void
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29 }
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30
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31 declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1
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32 declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1
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34 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
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35 attributes #1 = { nounwind readnone }
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36 attributes #2 = { nounwind }
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37