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annotate test/CodeGen/Hexagon/pic-regusage.ll @ 146:3fc4d5c3e21e

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set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 1172e4bd9c6f
children c2174574ed3a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s
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2
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3 ; Force the use of R14 (by clobbering everything else in the inline asm).
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4 ; Make sure that R14 is not set before the __save call (which will clobber
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5 ; R14, R15 and R28).
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6 ; CHECK: call __save_r16_through_r27
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7 ; CHECK: }
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8 ; CHECK: r14{{ *}}=
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9
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10 @.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
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11
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12 ; Function Attrs: nounwind optsize
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13 define i32 @_Z7testR14Pi(i32* nocapture %res) #0 {
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14 entry:
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15 %0 = load i32, i32* %res, align 4
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16 %1 = tail call { i32, i32 } asm "r0=$2\0A\09$1=add(r0,#$3)\0A\09$0=add(r0,#$4)\0A\09", "=r,=r,r,i,i,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27}"(i32 %0, i32 40, i32 50) #1
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17 %asmresult = extractvalue { i32, i32 } %1, 0
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18 %asmresult1 = extractvalue { i32, i32 } %1, 1
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19 store i32 %asmresult, i32* %res, align 4
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20 %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %asmresult1) #2
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21 %2 = load i32, i32* %res, align 4
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22 %call2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) #2
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23 ret i32 0
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24 }
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25
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26 ; Function Attrs: nounwind optsize
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27 declare i32 @printf(i8*, ...) #0
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28
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29 ; Same as above for R15.
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30 ; CHECK: call __save_r16_through_r27
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31 ; CHECK: }
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32 ; CHECK: r15{{ *}}=
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33
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34 ; Function Attrs: nounwind optsize
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35 define i32 @_Z7testR15Pi(i32* nocapture %res) #0 {
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36 entry:
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37 %0 = load i32, i32* %res, align 4
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38 %1 = tail call { i32, i32 } asm "r0=$2\0A\09$1=add(r0,#$3)\0A\09$0=add(r0,#$4)\0A\09", "=r,=r,r,i,i,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27}"(i32 %0, i32 40, i32 50) #1
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39 %asmresult = extractvalue { i32, i32 } %1, 0
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40 %asmresult1 = extractvalue { i32, i32 } %1, 1
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41 store i32 %asmresult, i32* %res, align 4
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42 %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %asmresult1) #2
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43 %2 = load i32, i32* %res, align 4
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44 %call2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) #2
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45 ret i32 0
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46 }
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47
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48 ; Same as above for R28.
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49 ; CHECK: call __save_r16_through_r27
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50 ; CHECK: }
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51 ; CHECK: r28{{ *}}=
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52
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53 ; Function Attrs: nounwind optsize
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54 define i32 @_Z7testR28Pi(i32* nocapture %res) #0 {
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55 entry:
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56 %0 = load i32, i32* %res, align 4
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57 %1 = tail call { i32, i32 } asm "r0=$2\0A\09$1=add(r0,#$3)\0A\09$0=add(r0,#$4)\0A\09", "=r,=r,r,i,i,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26}"(i32 %0, i32 40, i32 50) #1
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58 %asmresult = extractvalue { i32, i32 } %1, 0
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59 %asmresult1 = extractvalue { i32, i32 } %1, 1
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60 store i32 %asmresult, i32* %res, align 4
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61 %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %asmresult1) #2
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62 %2 = load i32, i32* %res, align 4
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63 %call2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) #2
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64 ret i32 0
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65 }
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66
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67 attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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68 attributes #1 = { nounwind }
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69 attributes #2 = { nounwind optsize }