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1 ; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 < %s -o - | FileCheck %s
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2
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3 define i64 @dext_add_zext(i32 signext %n) {
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4 entry:
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5 %add = add i32 %n, 1
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6 %res = zext i32 %add to i64
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7 ret i64 %res
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8
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9 ; CHECK-LABEL: dext_add_zext:
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10 ; CHECK: dext $[[R0:[0-9]+]], $[[R0:[0-9]+]], 0, 32
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11
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12 }
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13
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14 define i32 @ext_and24(i32 signext %a) {
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15 entry:
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16 %and = and i32 %a, 16777215
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17 ret i32 %and
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18
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19 ; CHECK-LABEL: ext_and24:
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20 ; CHECK: ext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 24
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21
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22 }
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23
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24 define i64 @dext_and32(i64 zeroext %a) {
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25 entry:
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26 %and = and i64 %a, 4294967295
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27 ret i64 %and
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28
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29 ; CHECK-LABEL: dext_and32:
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30 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32
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31
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32 }
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33
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34 define i64 @dext_and35(i64 zeroext %a) {
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35 entry:
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36 %and = and i64 %a, 34359738367
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37 ret i64 %and
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38
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39 ; CHECK-LABEL: dext_and35:
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40 ; CHECK: dextm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 35
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41
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42 }
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43
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44 define i64 @dext_and20(i64 zeroext %a) {
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45 entry:
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46 %and = and i64 %a, 1048575
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47 ret i64 %and
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48
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49 ; CHECK-LABEL: dext_and20:
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50 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 20
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51
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52 }
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53
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54 define i64 @dext_and16(i64 zeroext %a) {
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55 entry:
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56 %and = and i64 %a, 65535
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57 ret i64 %and
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58
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59 ; CHECK-LABEL: dext_and16:
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60 ; CHECK: andi $[[R0:[0-9]+]], $[[R1:[0-9]+]], 65535
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61
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62 }
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63
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64 define i64 @dext_lsr_and20(i64 zeroext %a) {
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65 entry:
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66 %shr = lshr i64 %a, 5
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67 %and = and i64 %shr, 1048575
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68 ret i64 %and
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69
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70 ; CHECK-LABEL: dext_lsr_and20:
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71 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 5, 20
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72
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73 }
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74
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75 define i64 @dext_lsr_and8(i64 zeroext %a) {
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76 entry:
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77 %shr = lshr i64 %a, 40
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78 %and = and i64 %shr, 255
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79 ret i64 %and
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80
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81 ; CHECK-LABEL: dext_lsr_and8:
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82 ; CHECK: dextu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 40, 8
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83
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84 }
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85
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86 define i64 @dext_zext(i32 signext %a) {
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87 entry:
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88 %conv = zext i32 %a to i64
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89 ret i64 %conv
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90
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91 ; CHECK-LABEL: dext_zext:
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92 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32
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93
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94 }
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95
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96 define i64 @dext_and_lsr(i64 zeroext %n) {
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97 entry:
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98 %and = lshr i64 %n, 8
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99 %shr = and i64 %and, 4095
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100 ret i64 %shr
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101
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102 ; CHECK-LABEL: dext_and_lsr:
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103 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 8, 12
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104
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105 }
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