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120
|
1 ; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP
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2 ; RUN: llc -march=mips -mcpu=mips32r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP
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3 ; RUN: llc -march=mips -mcpu=mips32r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,GPR32-TRAP
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4 ; RUN: llc -march=mips64 -mcpu=mips64 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP
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5 ; RUN: llc -march=mips64 -mcpu=mips64r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP
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6 ; RUN: llc -march=mips64 -mcpu=mips64r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
7
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|
120
|
8 ; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK
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9 ; RUN: llc -march=mips -mcpu=mips32r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK
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10 ; RUN: llc -march=mips -mcpu=mips32r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,NOCHECK
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11 ; RUN: llc -march=mips64 -mcpu=mips64 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
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12 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
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13 ; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
14
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77
|
15 ; FileCheck Prefixes:
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16 ; ALL - All targets
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17 ; ACC32 - Accumulator based multiply/divide on 32-bit targets
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18 ; ACC64 - Same as ACC32 but only for 64-bit targets
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19 ; GPR32 - GPR based multiply/divide on 32-bit targets
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20 ; GPR64 - Same as GPR32 but only for 64-bit targets
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21 ; ACC32-TRAP - Same as TRAP and ACC32 combined
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22 ; ACC64-TRAP - Same as TRAP and ACC64 combined
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23 ; GPR32-TRAP - Same as TRAP and GPR32 combined
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24 ; GPR64-TRAP - Same as TRAP and GPR64 combined
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25 ; NOCHECK - Division by zero will not be detected
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
26
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
27 @g0 = common global i32 0, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
28 @g1 = common global i32 0, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
29
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83
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30 define i32 @sdiv1(i32 signext %a0, i32 signext %a1) nounwind readnone {
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
31 entry:
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77
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32 ; ALL-LABEL: sdiv1:
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33
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34 ; ACC32: div $zero, $4, $5
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35 ; ACC32-TRAP: teq $5, $zero, 7
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36
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37 ; ACC64: div $zero, $4, $5
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38 ; ACC64-TRAP: teq $5, $zero, 7
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39
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40 ; GPR32: div $2, $4, $5
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41 ; GPR32-TRAP: teq $5, $zero, 7
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42
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43 ; GPR64: div $2, $4, $5
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44 ; GPR64-TRAP: teq $5, $zero, 7
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45
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46 ; NOCHECK-NOT: teq
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47
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48 ; ACC32: mflo $2
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49 ; ACC64: mflo $2
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50
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51 ; ALL: .end sdiv1
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52
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
53 %div = sdiv i32 %a0, %a1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
54 ret i32 %div
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
55 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
56
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83
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57 define i32 @srem1(i32 signext %a0, i32 signext %a1) nounwind readnone {
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
58 entry:
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77
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59 ; ALL-LABEL: srem1:
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60
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61 ; ACC32: div $zero, $4, $5
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62 ; ACC32-TRAP: teq $5, $zero, 7
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63
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64 ; ACC64: div $zero, $4, $5
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65 ; ACC64-TRAP: teq $5, $zero, 7
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66
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67 ; GPR32: mod $2, $4, $5
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68 ; GPR32-TRAP: teq $5, $zero, 7
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69
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70 ; GPR64: mod $2, $4, $5
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71 ; GPR64-TRAP: teq $5, $zero, 7
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72
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73 ; NOCHECK-NOT: teq
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74
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75 ; ACC32: mfhi $2
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76 ; ACC64: mfhi $2
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77
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78 ; ALL: .end srem1
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79
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
80 %rem = srem i32 %a0, %a1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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81 ret i32 %rem
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
82 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
83
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120
|
84 define i32 @udiv1(i32 signext %a0, i32 signext %a1) nounwind readnone {
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
85 entry:
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77
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86 ; ALL-LABEL: udiv1:
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87
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88 ; ACC32: divu $zero, $4, $5
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89 ; ACC32-TRAP: teq $5, $zero, 7
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90
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91 ; ACC64: divu $zero, $4, $5
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92 ; ACC64-TRAP: teq $5, $zero, 7
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93
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94 ; GPR32: divu $2, $4, $5
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95 ; GPR32-TRAP: teq $5, $zero, 7
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96
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97 ; GPR64: divu $2, $4, $5
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98 ; GPR64-TRAP: teq $5, $zero, 7
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99
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100 ; NOCHECK-NOT: teq
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101
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102 ; ACC32: mflo $2
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103 ; ACC64: mflo $2
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104
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105 ; ALL: .end udiv1
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
106 %div = udiv i32 %a0, %a1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
107 ret i32 %div
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
108 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
109
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120
|
110 define i32 @urem1(i32 signext %a0, i32 signext %a1) nounwind readnone {
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
111 entry:
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77
|
112 ; ALL-LABEL: urem1:
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113
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114 ; ACC32: divu $zero, $4, $5
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115 ; ACC32-TRAP: teq $5, $zero, 7
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116
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117 ; ACC64: divu $zero, $4, $5
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118 ; ACC64-TRAP: teq $5, $zero, 7
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119
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120 ; GPR32: modu $2, $4, $5
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121 ; GPR32-TRAP: teq $5, $zero, 7
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122
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123 ; GPR64: modu $2, $4, $5
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124 ; GPR64-TRAP: teq $5, $zero, 7
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125
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126 ; NOCHECK-NOT: teq
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127
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128 ; ACC32: mfhi $2
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129 ; ACC64: mfhi $2
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130
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131 ; ALL: .end urem1
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132
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
133 %rem = urem i32 %a0, %a1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
134 ret i32 %rem
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
135 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
136
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83
|
137 define i32 @sdivrem1(i32 signext %a0, i32 signext %a1, i32* nocapture %r) nounwind {
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
138 entry:
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|
77
|
139 ; ALL-LABEL: sdivrem1:
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140
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141 ; ACC32: div $zero, $4, $5
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142 ; ACC32-TRAP: teq $5, $zero, 7
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143 ; NOCHECK-NOT: teq
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144 ; ACC32: mflo $2
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145 ; ACC32: mfhi $[[R0:[0-9]+]]
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146 ; ACC32: sw $[[R0]], 0(${{[0-9]+}})
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147
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148 ; ACC64: div $zero, $4, $5
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149 ; ACC64-TRAP: teq $5, $zero, 7
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150 ; NOCHECK-NOT: teq
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|
151 ; ACC64: mflo $2
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152 ; ACC64: mfhi $[[R0:[0-9]+]]
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153 ; ACC64: sw $[[R0]], 0(${{[0-9]+}})
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154
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|
120
|
155 ; GPR32-DAG: mod $[[R0:[0-9]+]], $4, $5
|
|
77
|
156 ; GPR32-TRAP: teq $5, $zero, 7
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157 ; NOCHECK-NOT: teq
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|
158 ; GPR32: sw $[[R0]], 0(${{[0-9]+}})
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159 ; GPR32-DAG: div $2, $4, $5
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160 ; GPR32-TRAP: teq $5, $zero, 7
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161
|
|
120
|
162 ; GPR64-DAG: mod $[[R0:[0-9]+]], $4, $5
|
|
77
|
163 ; GPR64-TRAP: teq $5, $zero, 7
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164 ; NOCHECK-NOT: teq
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165 ; GPR64: sw $[[R0]], 0(${{[0-9]+}})
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166 ; GPR64-DAG: div $2, $4, $5
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167 ; GPR64-TRAP: teq $5, $zero, 7
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168 ; NOCHECK-NOT: teq
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169
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170 ; ALL: .end sdivrem1
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171
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
172 %rem = srem i32 %a0, %a1
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
173 store i32 %rem, i32* %r, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
174 %div = sdiv i32 %a0, %a1
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
175 ret i32 %div
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
176 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
177
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|
120
|
178 define i32 @udivrem1(i32 signext %a0, i32 signext %a1, i32* nocapture %r) nounwind {
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
179 entry:
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|
77
|
180 ; ALL-LABEL: udivrem1:
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181
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182 ; ACC32: divu $zero, $4, $5
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183 ; ACC32-TRAP: teq $5, $zero, 7
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184 ; NOCHECK-NOT: teq
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185 ; ACC32: mflo $2
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186 ; ACC32: mfhi $[[R0:[0-9]+]]
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187 ; ACC32: sw $[[R0]], 0(${{[0-9]+}})
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188
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189 ; ACC64: divu $zero, $4, $5
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190 ; ACC64-TRAP: teq $5, $zero, 7
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191 ; NOCHECK-NOT: teq
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192 ; ACC64: mflo $2
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193 ; ACC64: mfhi $[[R0:[0-9]+]]
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194 ; ACC64: sw $[[R0]], 0(${{[0-9]+}})
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195
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120
|
196 ; GPR32-DAG: modu $[[R0:[0-9]+]], $4, $5
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|
77
|
197 ; GPR32-TRAP: teq $5, $zero, 7
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|
120
|
198 ; GPR32: sw $[[R0]], 0(${{[0-9]+}})
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|
77
|
199 ; NOCHECK-NOT: teq
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200 ; GPR32-DAG: divu $2, $4, $5
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201 ; GPR32-TRAP: teq $5, $zero, 7
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202 ; NOCHECK-NOT: teq
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203
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|
120
|
204 ; GPR64-DAG: modu $[[R0:[0-9]+]], $4, $5
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|
77
|
205 ; GPR64-TRAP: teq $5, $zero, 7
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206 ; NOCHECK-NOT: teq
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|
207 ; GPR64: sw $[[R0]], 0(${{[0-9]+}})
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208 ; GPR64-DAG: divu $2, $4, $5
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209 ; GPR64-TRAP: teq $5, $zero, 7
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210 ; NOCHECK-NOT: teq
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211
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212 ; ALL: .end udivrem1
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213
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
214 %rem = urem i32 %a0, %a1
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
215 store i32 %rem, i32* %r, align 4
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
216 %div = udiv i32 %a0, %a1
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
217 ret i32 %div
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
218 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
219
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|
77
|
220 ; FIXME: It's not clear what this is supposed to test.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
221 define i32 @killFlags() {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
222 entry:
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|
95
|
223 %0 = load i32, i32* @g0, align 4
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|
224 %1 = load i32, i32* @g1, align 4
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
225 %div = sdiv i32 %0, %1
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
226 ret i32 %div
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
227 }
|
|
77
|
228
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|
|
229 define i64 @sdiv2(i64 %a0, i64 %a1) nounwind readnone {
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230 entry:
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|
231 ; ALL-LABEL: sdiv2:
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232
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|
233 ; ACC32: lw $25, %call16(__divdi3)(
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234 ; ACC32: jalr $25
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235
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236 ; ACC64: ddiv $zero, $4, $5
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237 ; ACC64-TRAP: teq $5, $zero, 7
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238
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239 ; GPR64: ddiv $2, $4, $5
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|
240 ; GPR64-TRAP: teq $5, $zero, 7
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241
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242 ; NOCHECK-NOT: teq
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243
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|
244 ; ACC64: mflo $2
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|
|
245
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|
246 ; ALL: .end sdiv2
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247
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|
248 %div = sdiv i64 %a0, %a1
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|
|
249 ret i64 %div
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|
|
250 }
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251
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|
252 define i64 @srem2(i64 %a0, i64 %a1) nounwind readnone {
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253 entry:
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254 ; ALL-LABEL: srem2:
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255
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|
|
256 ; ACC32: lw $25, %call16(__moddi3)(
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|
257 ; ACC32: jalr $25
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|
|
258
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|
259 ; ACC64: div $zero, $4, $5
|
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|
260 ; ACC64-TRAP: teq $5, $zero, 7
|
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261
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|
262 ; GPR64: dmod $2, $4, $5
|
|
|
263 ; GPR64-TRAP: teq $5, $zero, 7
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|
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264
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|
|
265 ; NOCHECK-NOT: teq
|
|
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266
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|
|
267 ; ACC64: mfhi $2
|
|
|
268
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|
269 ; ALL: .end srem2
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270
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|
|
271 %rem = srem i64 %a0, %a1
|
|
|
272 ret i64 %rem
|
|
|
273 }
|
|
|
274
|
|
|
275 define i64 @udiv2(i64 %a0, i64 %a1) nounwind readnone {
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|
|
276 entry:
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|
277 ; ALL-LABEL: udiv2:
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|
278
|
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279 ; ACC32: lw $25, %call16(__udivdi3)(
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280 ; ACC32: jalr $25
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281
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282 ; ACC64: divu $zero, $4, $5
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283 ; ACC64-TRAP: teq $5, $zero, 7
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284
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285 ; GPR64: ddivu $2, $4, $5
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286 ; GPR64-TRAP: teq $5, $zero, 7
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287
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288 ; NOCHECK-NOT: teq
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289
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290 ; ACC64: mflo $2
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291
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292 ; ALL: .end udiv2
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293 %div = udiv i64 %a0, %a1
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294 ret i64 %div
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295 }
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296
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297 define i64 @urem2(i64 %a0, i64 %a1) nounwind readnone {
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298 entry:
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299 ; ALL-LABEL: urem2:
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300
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301 ; ACC32: lw $25, %call16(__umoddi3)(
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302 ; ACC32: jalr $25
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303
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304 ; ACC64: divu $zero, $4, $5
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305 ; ACC64-TRAP: teq $5, $zero, 7
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306
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307 ; GPR64: dmodu $2, $4, $5
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308 ; GPR64-TRAP: teq $5, $zero, 7
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309
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310 ; NOCHECK-NOT: teq
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311
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312 ; ACC64: mfhi $2
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313
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314 ; ALL: .end urem2
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315
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316 %rem = urem i64 %a0, %a1
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317 ret i64 %rem
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318 }
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319
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320 define i64 @sdivrem2(i64 %a0, i64 %a1, i64* nocapture %r) nounwind {
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321 entry:
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322 ; ALL-LABEL: sdivrem2:
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323
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324 ; sdivrem2 is too complex to effectively check. We can at least check for the
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325 ; calls though.
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326 ; ACC32: lw $25, %call16(__moddi3)(
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327 ; ACC32: jalr $25
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328 ; ACC32: lw $25, %call16(__divdi3)(
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329 ; ACC32: jalr $25
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330
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331 ; ACC64: ddiv $zero, $4, $5
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332 ; ACC64-TRAP: teq $5, $zero, 7
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333 ; NOCHECK-NOT: teq
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334 ; ACC64: mflo $2
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335 ; ACC64: mfhi $[[R0:[0-9]+]]
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336 ; ACC64: sd $[[R0]], 0(${{[0-9]+}})
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337
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120
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338 ; GPR64-DAG: dmod $[[R0:[0-9]+]], $4, $5
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77
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339 ; GPR64-TRAP: teq $5, $zero, 7
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340 ; NOCHECK-NOT: teq
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341 ; GPR64: sd $[[R0]], 0(${{[0-9]+}})
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342
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343 ; GPR64-DAG: ddiv $2, $4, $5
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344 ; GPR64-TRAP: teq $5, $zero, 7
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345 ; NOCHECK-NOT: teq
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346
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347 ; ALL: .end sdivrem2
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348
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349 %rem = srem i64 %a0, %a1
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350 store i64 %rem, i64* %r, align 8
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351 %div = sdiv i64 %a0, %a1
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352 ret i64 %div
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353 }
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354
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355 define i64 @udivrem2(i64 %a0, i64 %a1, i64* nocapture %r) nounwind {
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356 entry:
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357 ; ALL-LABEL: udivrem2:
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358
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359 ; udivrem2 is too complex to effectively check. We can at least check for the
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360 ; calls though.
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361 ; ACC32: lw $25, %call16(__umoddi3)(
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362 ; ACC32: jalr $25
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363 ; ACC32: lw $25, %call16(__udivdi3)(
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364 ; ACC32: jalr $25
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365
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366 ; ACC64: ddivu $zero, $4, $5
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367 ; ACC64-TRAP: teq $5, $zero, 7
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368 ; NOCHECK-NOT: teq
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369 ; ACC64: mflo $2
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370 ; ACC64: mfhi $[[R0:[0-9]+]]
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371 ; ACC64: sd $[[R0]], 0(${{[0-9]+}})
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372
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373 ; GPR64: dmodu $[[R0:[0-9]+]], $4, $5
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374 ; GPR64-TRAP: teq $5, $zero, 7
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375 ; NOCHECK-NOT: teq
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376 ; GPR64: sd $[[R0]], 0(${{[0-9]+}})
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377
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378 ; GPR64-DAG: ddivu $2, $4, $5
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379 ; GPR64-TRAP: teq $5, $zero, 7
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380 ; NOCHECK-NOT: teq
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381
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382 ; ALL: .end udivrem2
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383
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384 %rem = urem i64 %a0, %a1
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385 store i64 %rem, i64* %r, align 8
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386 %div = udiv i64 %a0, %a1
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387 ret i64 %div
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388 }
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