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annotate test/CodeGen/Mips/seleq.ll @ 146:3fc4d5c3e21e

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set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 7d135dc70f03
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
100
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
1 ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
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2
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3 @t = global i32 10, align 4
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4 @f = global i32 199, align 4
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5 @a = global i32 1, align 4
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6 @b = global i32 10, align 4
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7 @c = global i32 1, align 4
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8 @z1 = common global i32 0, align 4
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9 @z2 = common global i32 0, align 4
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10 @z3 = common global i32 0, align 4
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parents:
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11 @z4 = common global i32 0, align 4
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12
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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13 define void @calc_seleq() nounwind {
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14 entry:
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afa8332a0e37 LLVM 3.8
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parents: 83
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15 %0 = load i32, i32* @a, align 4
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parents: 83
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16 %1 = load i32, i32* @b, align 4
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17 %cmp = icmp eq i32 %0, %1
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18 br i1 %cmp, label %cond.true, label %cond.false
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19
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20 cond.true: ; preds = %entry
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21 %2 = load i32, i32* @f, align 4
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22 br label %cond.end
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23
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24 cond.false: ; preds = %entry
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parents: 83
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25 %3 = load i32, i32* @t, align 4
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26 br label %cond.end
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27
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28 cond.end: ; preds = %cond.false, %cond.true
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29 %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ]
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30 store i32 %cond, i32* @z1, align 4
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parents: 83
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31 %4 = load i32, i32* @b, align 4
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32 %5 = load i32, i32* @a, align 4
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33 %cmp1 = icmp eq i32 %4, %5
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34 br i1 %cmp1, label %cond.true2, label %cond.false3
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35
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36 cond.true2: ; preds = %cond.end
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37 %6 = load i32, i32* @f, align 4
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38 br label %cond.end4
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39
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40 cond.false3: ; preds = %cond.end
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parents: 83
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41 %7 = load i32, i32* @t, align 4
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42 br label %cond.end4
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43
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44 cond.end4: ; preds = %cond.false3, %cond.true2
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45 %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ]
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46 store i32 %cond5, i32* @z2, align 4
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parents: 83
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47 %8 = load i32, i32* @c, align 4
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parents: 83
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48 %9 = load i32, i32* @a, align 4
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49 %cmp6 = icmp eq i32 %8, %9
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50 br i1 %cmp6, label %cond.true7, label %cond.false8
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51
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52 cond.true7: ; preds = %cond.end4
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parents: 83
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53 %10 = load i32, i32* @t, align 4
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54 br label %cond.end9
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56 cond.false8: ; preds = %cond.end4
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57 %11 = load i32, i32* @f, align 4
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58 br label %cond.end9
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60 cond.end9: ; preds = %cond.false8, %cond.true7
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61 %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ]
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62 store i32 %cond10, i32* @z3, align 4
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parents: 83
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63 %12 = load i32, i32* @a, align 4
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parents: 83
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64 %13 = load i32, i32* @c, align 4
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65 %cmp11 = icmp eq i32 %12, %13
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66 br i1 %cmp11, label %cond.true12, label %cond.false13
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67
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68 cond.true12: ; preds = %cond.end9
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parents: 83
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69 %14 = load i32, i32* @t, align 4
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70 br label %cond.end14
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72 cond.false13: ; preds = %cond.end9
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parents: 83
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73 %15 = load i32, i32* @f, align 4
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74 br label %cond.end14
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75
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76 cond.end14: ; preds = %cond.false13, %cond.true12
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77 %cond15 = phi i32 [ %14, %cond.true12 ], [ %15, %cond.false13 ]
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78 store i32 %cond15, i32* @z4, align 4
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79 ret void
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80 }
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82 attributes #0 = { nounwind "target-cpu"="mips32" "target-features"="+o32,+mips32" }
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84 ; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
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85 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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87 ; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
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88 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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90 ; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
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91 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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93 ; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
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94 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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95