annotate test/CodeGen/RISCV/inline-asm.ll @ 146:3fc4d5c3e21e

set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 3a76565eade5
children c2174574ed3a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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3 ; RUN: | FileCheck -check-prefix=RV32I %s
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4
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5 @gi = external global i32
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6
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7 define i32 @constraint_r(i32 %a) {
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8 ; RV32I-LABEL: constraint_r:
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9 ; RV32I: # %bb.0:
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10 ; RV32I-NEXT: lui a1, %hi(gi)
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11 ; RV32I-NEXT: addi a1, a1, %lo(gi)
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12 ; RV32I-NEXT: lw a1, 0(a1)
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13 ; RV32I-NEXT: #APP
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14 ; RV32I-NEXT: add a0, a0, a1
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15 ; RV32I-NEXT: #NO_APP
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16 ; RV32I-NEXT: ret
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17 %1 = load i32, i32* @gi
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18 %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
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19 ret i32 %2
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20 }
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21
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22 define i32 @constraint_i(i32 %a) {
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23 ; RV32I-LABEL: constraint_i:
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24 ; RV32I: # %bb.0:
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25 ; RV32I-NEXT: #APP
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26 ; RV32I-NEXT: addi a0, a0, 113
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27 ; RV32I-NEXT: #NO_APP
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28 ; RV32I-NEXT: ret
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29 %1 = load i32, i32* @gi
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30 %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
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31 ret i32 %2
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32 }
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33
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34 define void @constraint_m(i32* %a) {
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35 ; RV32I-LABEL: constraint_m:
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36 ; RV32I: # %bb.0:
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37 ; RV32I-NEXT: #APP
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38 ; RV32I-NEXT: #NO_APP
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39 ; RV32I-NEXT: ret
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40 call void asm sideeffect "", "=*m"(i32* %a)
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41 ret void
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42 }
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43
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44 define i32 @constraint_m2(i32* %a) {
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45 ; RV32I-LABEL: constraint_m2:
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46 ; RV32I: # %bb.0:
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47 ; RV32I-NEXT: #APP
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48 ; RV32I-NEXT: lw a0, 0(a0)
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49 ; RV32I-NEXT: #NO_APP
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50 ; RV32I-NEXT: ret
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51 %1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind
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52 ret i32 %1
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53 }
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54
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55 ; TODO: expend tests for more complex constraints, out of range immediates etc